IDTCSP2510DPGI datasheet(3/9 Pages) IDT

Part #	IDTCSP2510DPGI

Description	3.3V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER

Download	9 Pages

Scroll/Zoom	100%

Manufacturer	IDT [Integrated Device Technology]

Direct Link	http://www.idt.com

Logo

3 / 9 page

3

0

°CTO85°CTEMPERATURERANGE

IDTCSP2510D

3.3V PHASE-LOCK LOOP CLOCK DRIVER

STATIC FUNCTION TABLE (AVDD=0V)

DYNAMIC FUNCTION TABLE (AVDD=3.3V)

PIN DESCRIPTION

Terminal

Name

No.

Type

Description

CLK

24

I

Clockinput. CLKprovidestheclocksignaltobedistributedbytheCSP2510Dclockdriver. CLKisusedtoprovidethereferencesignal

totheintegratedPLLthatgeneratestheclockoutputsignals.CLKmusthaveafixedfrequencyandfixedphaseforthePLLtoobtainphase

lock. OncethecircuitispoweredupandavalidCLKsignalisapplied,astabilizationtimeisrequiredforthePLLtophaselockthefeedback

signaltoitsreferencesignal.

FBIN

13

I

Feedbackinput. FBINprovidesthefeedbacksignaltotheinternalPLL. FBINmustbehard-wiredtoFBOUTtocompletethePLL. The

integrated PLL synchronizes CLK and FBIN so that there is nominally zero phase error between CLK and FBIN.

G

11

I

Outputbankenable. GistheoutputenableforoutputsY(0:9). WhenGislow,outputsY(0:9)aredisabledtoalogic-lowstate. When

G is high, all outputs Y(0:9) are enabled and switch at the same frequency as CLK.

FBOUT

12

O

Feedback output. FBOUT is dedicated for external feedback. It switches at the same frequency as CLK. When externally wired to

FBIN, FBOUT completes the feedback loop of the PLL.

Y (0:9)

3, 4, 5, 8, 9,

O

Clockoutputs. Theseoutputsprovidelow-skewcopiesofCLK. OutputbankY(0:9)isenabledviatheGinput. Theseoutputscanbe

15, 16, 17,

disabledtoalogic-lowstatebyde-assertingtheGcontrolinput.

20,21

AVDD

23

Power

Analog power supply. AVDD provides the power reference for the analog circuitry. In addition, AVDD can be used to bypass the PLL

for test purposes. When AVDD is strapped to ground, PLL is bypassed and CLK is buffered directly to the device outputs.

AGND

1

Ground

Analog ground. AGND provides the ground reference for the analog circuitry.

VDD

2, 10, 14, 22 Power

Power supply

GND

6, 7, 18, 19 Ground

Ground

Inputs

Outputs

G

CLK

Y (0:9)

FBOUT

LL

L

LH

L

H

HH

H

HL

L

H

running

Inputs

Outputs

G

CLK

Y (0:9)

FBOUT

XL

L

running

L

runningin

phase with CLK

LH

L

H

running

runningin

phase with CLK

HH

H

Similar Part No. - IDTCSP2510DPGI

Manufacturer	Part #	Datasheet	Description
Integrated Device Techn...	IDTCSP2510DPGI	65Kb / 9P	3.3V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER

More results

Similar Description - IDTCSP2510DPGI

Manufacturer	Part #	Datasheet	Description
Renesas Technology Corp	CSP2510C	262Kb / 10P	3.3V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER NOVEMBER 2008
Integrated Device Techn...	IDTCSP2510D	65Kb / 9P	3.3V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER
Renesas Technology Corp	CSP2510D	251Kb / 10P	3.3V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER OCTOBER 2001
Integrated Device Techn...	IDTCSP2510C	63Kb / 9P	3.3V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER
	IDT5V9352	81Kb / 10P	3.3V/2.5V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER
	IDT5V2528	61Kb / 7P	2.5V / 3.3V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER
	IDT2309	125Kb / 10P	3.3V ZERO DELAY CLOCK BUFFER Phase-Lock Loop Clock Distribution
Integrated Circuit Syst...	ICS93705	65Kb / 7P	DDR Phase Lock Loop Zero Delay Clock Buffer
Renesas Technology Corp	ICS93705	343Kb / 9P	DDR Phase Lock Loop Zero Delay Clock Buffer 2019
Integrated Circuit Syst...	ICS93735	126Kb / 7P	DDR Phase Lock Loop Zero Delay Clock Buffer

More results

IDTCSP2510DPGI Datasheet(PDF) 3 Page - Integrated Device Technology

IDTCSP2510DPGI Datasheet(HTML) 3 Page - Integrated Device Technology

Similar Part No. - IDTCSP2510DPGI

Similar Description - IDTCSP2510DPGI

Html Pages

1 2 3 4 5 6 7 8 9

Datasheet Download

Link URL