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IDT72V275L15PF Datasheet(PDF) 2 Page - Integrated Device Technology |
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IDT72V275L15PF Datasheet(HTML) 2 Page - Integrated Device Technology |
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2 / 25 page  2 COMMERCIALANDINDUSTRIALTEMPERATURERANGE IDT72V275/72V285 PIN CON.IGURATIONS TQFP (PN64-1, order code: PF) STQFP (PP64-1, order code: TF) TOP VIEW DESCRIPTION (Continued) PIN 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 WEN SEN DC(1) VCC GND D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Q17 Q16 GND Q15 Q14 VCC Q13 Q12 Q11 GND Q10 Q9 Q8 Q7 Q6 GND 4512 drw 02 TheinputportiscontrolledbyaWriteClock(WCLK)inputandaWriteEnable ( WEN)input. DataiswrittenintotheFIFOoneveryrisingedgeofWCLKwhen WENisasserted.TheoutputportiscontrolledbyaReadClock(RCLK)input and Read Enable ( REN) input. Data is read from the FIFO on every rising edgeofRCLKwhen RENisasserted. AnOutputEnable(OE)inputisprovided for three-state control of the outputs. The frequencies of both the RCLK and the WCLK signals may vary from 0 tofMAXwithcompleteindependence. Therearenorestrictionsonthefrequency of the one clock input with respect to the other. There are two possible timing modes of operation with these devices: IDT Standard mode and First Word Fall Through (FWFT) mode. InIDTStandardmode,thefirstwordwrittentoanemptyFIFOwillnotappear on the data output lines unless a specific read operation is performed. A read operation,whichconsistsofactivating RENandenablingarisingRCLKedge, will shift the word from internal memory to the data output lines. In FWFT mode, the first word written to an empty FIFO is clocked directly to the data output lines after three transitions of the RCLK signal. A RENdoes not have to be asserted for accessing the first word. However, subsequent words written to the FIFO do require a LOW on REN foraccess. Thestateof the FWFT/SI input during Master Reset determines the timing mode in use. For applications requiring more data storage capacity than a single FIFO canprovide,theFWFTtimingmodepermitsdepthexpansionbychainingFIFOs in series (i.e. the data outputs of one FIFO are connected to the corresponding data inputs of the next). No external logic is required. NOTE: 1. DC = Don’t Care. Must be tied to GND or VCC, cannot be left open. |
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