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5962-0151101 Datasheet(PDF) 10 Page - Aeroflex Circuit Technology |
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5962-0151101 Datasheet(HTML) 10 Page - Aeroflex Circuit Technology |
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10 / 14 page  10 t EFDX Assumptions & Notes: 1. G < V IL (max). If G > V IH (min) then Q n(7:0) will be in three-state for the entire cycle. 2. Either En scenario above can occur. 3 . G high for t AVAV cycle. A(18:0) Figure 5b. SRAM Write Cycle 2: Chip Enable - Controlled Access Wn En Dn(7:0) APPLIED DATA En Qn(7:0) tWLQZ t ETEF tWLEF tDVEF t AVAV3 tAVET t AVET tETEF tEFAX tEFAX or Notes: 1. 50pF including scope probe and test socket capacitance. 2. Measurement of data output occurs at the low to high or high to low transition mid-point (i.e., CMOS input = V DD/2). 90% Figure 6. AC Test Loads and Input Waveforms Input Pulses 10% < 5ns < 5ns VLOAD = 1.55V 300 ohms 50pF CMOS 0.5V VDD-0.05V 10% |
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