128K x 8 High-Speed CMOS EPROM
fax id: 3023
CY27H010
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
August 1994 – Revised March 1997
1CY 27H0 10
Features
• CMOS for optimum speed/power
• High speed
—tAA = 25 ns max. (commercial)
—tAA = 35 ns max. (military)
• Low power
— 275 mW max.
— Less than 85 mW when deselected
• Byte-wide memory organization
• 100% reprogrammable in thewindowed package
• EPROM technology
• Capable of withstanding >2001V static discharge
• Available in
— 32-pin PLCC
— 32-pin TSOP-I
— 32-pin, 600-mil plastic or hermetic DIP
— 32-pin hermetic LCC
Functional Description
The CY27H010 is a high-performance, 1-megabit CMOS
EPROM organized in 128 Kbytes. It is available in indus-
try-standard 32-pin, 600-mil DIP, LCC, PLCC, and TSOP-I
packages.
These devices offer high-density storage com-
bined with 40-MHz performance. The CY27H010 is available
in windowed and opaque packages. Windowed packages al-
low the device to be erased with UV light for 100% re-
programmability.
The CY27H010 is equipped with a power-down chip enable
(CE) input and output enable (OE). When CE is deasserted,
the device powers down to a low-power stand-by mode. The
OE pin three-states the outputs without putting the device into
stand-by mode. While CE offers lower power, OE provides a
more rapid transition to and from three-stated outputs.
The memory cells utilize proven EPROM floating-gate technol-
ogy and byte-wide intelligent programming algorithms. The
EPROM cell requires only 12.75 V for the supervoltage and
low programming current allows for gang programming. The
device allows for each memory location to be tested 100%,
because each location is written to, erased, and repeatedly
exercised prior to encapsulation. Each device is also tested
for AC performance to guarantee that the product will meet DC
and AC specification limits after customer programming.
The CY27H010 is read by asserting both the CE and the OE
inputs. The contents of the memory location selected by the
address on inputs A16–A0 will appear at the outputs O7–O0.
Logic Block Diagram
Pin Configurations
1
2
3
4
5
6
7
8
9
10
11
14
19
20
24
23
22
21
25
28
27
26
Top View
DIP
12
13
29
32
31
30
16
15
17
18
GND
A16
A15
A12
A7
A6
A5
A4
A3
A14
VCC
PGM
A13
A8
A9
O7
O6
O5
O4
A2
VPP
O0
O1
O2
CE
OE
A10
O3
A1
A0
A11
NC
H010–1
H010–2
12
O0
31
4
5
6
7
8
9
10
32 1
30
13
14151617
26
25
24
23
22
21
11
A7
A6
A5
A4
A3
A2
A1
A10
A13
A8
A9
OE
CE
O7
Top View
LCC/PLCC
A14
A11
181920
27
28
29
32
H010–3
A0
PROGRAMMABLE
ARRAY
O0
O1
O7
O2
O4
O3
O5
O6
ADDRESS
DECODER
A0
A1
A2
A3
A4
A5
A6
A8
A7
MULTIPLEXER
A9
A10
A11
A12
A13
A14
A15
A16
OUTPUT ENABLE
DECODER
CE
OE
POWER DOWN