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68HC705H12 Datasheet(PDF) 10 Page - Motorola, Inc |
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68HC705H12 Datasheet(HTML) 10 Page - Motorola, Inc |
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10 / 196 page  Table of Contents General Release Specification MC68HC(7)05H12 — Rev. 1.0 8 Table of Contents MOTOROLA 10.5.2 SPI Status Register (SPSR) . . . . . . . . . . . . . . . . . . . . . . . 123 10.5.3 SPI Data I/O Register (SPDAT) . . . . . . . . . . . . . . . . . . . . 124 10.6 SPI During WAIT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Section 11. Serial Communications Interface (SCI) 11.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 11.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 11.3 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 11.4 Receiver Wake-up Operation . . . . . . . . . . . . . . . . . . . . . . . . . 130 11.4.1 Idle Line Wake-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 11.4.2 Address Mark Wake-up. . . . . . . . . . . . . . . . . . . . . . . . . . . 131 11.5 Receive Data (RDI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 11.6 Start Bit Detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 11.7 Transmit Data (TDO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 11.8 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 11.8.1 Serial Communications Data Register (SCDAT). . . . . . . . 135 11.8.2 Serial Communications Control Register 1 (SCCR1) . . . . 136 11.8.3 Serial Communications Control Register 2 (SCCR2) . . . . 137 11.8.4 Serial Communications Status Register (SCSR) . . . . . . . 138 11.8.5 Baud Rate Register (BAUD) . . . . . . . . . . . . . . . . . . . . . . . 140 11.9 SCI During WAIT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 Section 12. Analog to Digital Converter 12.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 12.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 12.3 A/D Principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 12.4 A/D Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 12.5 Internal and Master Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . 145 12.6 A/D Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 12.6.1 A/D Status and Control Register (ADSCR) . . . . . . . . . . . . 146 12.6.2 A/D Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 12.7 A/D During WAIT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 12.8 Analog Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 |
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