M-NARA (AED30A)

3. FUNCTIONAL DESCRIPTION

3.1 Overview

M-NARA makes a low power operation on encoding/decoding with MP3 bitstream data. It has compactly-

made hardwired core that can operate at low frequency. Due to that, power consumption is less than any other

DSP encoder/decoder. With this architecture, there is no process to download the MP3 program.

3.2 Architecture

EXTERNAL

MEMORY

MCU

MP3

ENCODER

MP3

DECODER

M-NARA

PLL

OSC.

CRY.

PLL I/F

I2C I/F

BI2S I/F

PIO I/F

AI2S I/F

EXTERNAL

DAC

EXTERNAL

ADC

AI2S I/F

ETC. Pins

3.3 Internal PLL

The internal PLL is a low voltage, low cost, multi-clock generator. This can generate system clock and variou

s tempo clocks such as

±5%, ±10%, ±15%, and ±20% offset against system clock. The input system clock

is 12.288MHz.

3.4 External Audio Codec(ADC, DAC)

There is a I2S interface for the external AD/DA.

3.5 MPEG Codec/Arithmetic Logic/RAM

The MPEG codec is the MPEG1/2 layer3 encoder/decoder. The features of encoder/decoder are described at

“2. FEATURES”.

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