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BDGLA16NB Datasheet(PDF) 6 Page - Agere Systems |
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BDGLA16NB Datasheet(HTML) 6 Page - Agere Systems |
6 / 16 page 6 Agere Systems Inc. Data Sheet January 1999 BDG1A, BDP1A, BDGLA, BPNGA, BPNPA, and BPPGA Quad Differential Drivers Timing Characteristics (continued) 12-2677F Figure 2. Driver Propagation-Delay Timing 12-2268.dC * E2 = 1 while E1 changes state. † E1 = 0 while E2 changes state. Note: In the third state, both outputs (i.e., OUTPUT and OUTPUT) are 0.2 V below the low state. Figure 3. Driver Enable and Disable Timing for a High Input INPUT TRANSITION OUTPUTS OUTPUT OUTPUT OUTPUT ttLH tPHL ttHL tPLH tPHH tPLL tP2 tP1 20% 80% 20% 80% 2.4 V 1.5 V 0.4 V VOH VOL VOH (VOH + VOL)/2 VOL VOH (VOH + VOL)/2 VOL VOH VOL E1* OUTPUT OUTPUT tPHZ tPZH tPLZ tPZL 3.0 V 1.3 V 0.0 V VOH VOL + 0.2 V VOL VOL – 0.1 V VOL VOL – 0.1 V E2† 3.0 V 1.3 V 0.0 V |
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