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ISPGAL22V10B-7LJ Datasheet(PDF) 1 Page - Lattice Semiconductor |
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ISPGAL22V10B-7LJ Datasheet(HTML) 1 Page - Lattice Semiconductor |
1 / 15 page Specifications ispGAL22V10 1 • IN-SYSTEM PROGRAMMABLE™ (5-V ONLY) — 4-Wire Serial Programming Interface — Minimum 10,000 Program/Erase Cycles — Built-in Pull-Down on SDI Pin Eliminates Discrete Resistor on Board (ispGAL22V10C Only) • HIGH PERFORMANCE E2CMOS® TECHNOLOGY — 7.5 ns Maximum Propagation Delay — Fmax = 111 MHz — 5 ns Maximum from Clock Input to Data Output — UltraMOS® Advanced CMOS Technology • ACTIVE PULL-UPS ON ALL LOGIC INPUT AND I/O PINS • COMPATIBLE WITH STANDARD 22V10 DEVICES — Fully Function/Fuse-Map/Parametric Compatible with Bipolar and CMOS 22V10 Devices •E2 CELL TECHNOLOGY — In-System Programmable Logic — 100% Tested/100% Yields — High Speed Electrical Erasure (<100ms) — 20 Year Data Retention • TEN OUTPUT LOGIC MACROCELLS — Maximum Flexibility for Complex Logic Designs • APPLICATIONS INCLUDE: — DMA Control — State Machine Control — High Speed Graphics Processing — Software-Driven Hardware Configuration • ELECTRONIC SIGNATURE FOR IDENTIFICATION DESCRIPTION The ispGAL22V10, at 7.5ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the industry's first in-system programmable 22V10 device. E2 technology of- fers high speed (<100ms) erase times, providing the ability to re- program or reconfigure the device quickly and efficiently. The generic architecture provides maximum design flexibility by allowing the Output Logic Macrocell (OLMC) to be configured by the user. The ispGAL22V10 is fully function/fuse map/parametric compatible with standard bipolar and CMOS 22V10 devices. The standard PLCC package provides the same functional pinout as the standard 22V10 PLCC package with No-Connect pins being used for the ISP interface signals. Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during manufacture. As a result, Lattice Semiconductor delivers 100% field programmability and functionality of all GAL products. In addition, 10,000 erase/write cycles and data retention in excess of 20 years are specified. FUNCTIONAL BLOCK DIAGRAM FEATURES PIN CONFIGURATION I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q SDO SDI MODE SCLK I/CLK I I I I I I I I I I RESET PRESET 8 10 12 14 16 16 14 12 10 8 OLMC OLMC OLMC OLMC OLMC OLMC OLMC OLMC OLMC OLMC PROGRAMMING LOGIC I ispGAL22V10 In-System Programmable E2CMOS PLD Generic Array Logic™ Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. July 1997 Tel. (503) 681-0118; 1-888-ISP-PLDS; FAX (503) 681-3037; http://www.latticesemi.com PLCC SDO I/O/Q I/O/Q I/O/Q 22 8 I I MODE I I I 5 11 14 16 19 25 4 7 9 12 18 21 23 26 I I/O/Q I/O/Q I/O/Q Vcc I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q SDO I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I SDI SCLK I/CLK I I I I I MODE I I I I I GND 1 7 14 28 22 15 ispGAL 22V10 Top View SSOP ispGAL22V10 Top View isp22v10_02 |
Similar Part No. - ISPGAL22V10B-7LJ |
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Similar Description - ISPGAL22V10B-7LJ |
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