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M11B11664A-35J Datasheet(PDF) 6 Page - List of Unclassifed Manufacturers |
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M11B11664A-35J Datasheet(HTML) 6 Page - List of Unclassifed Manufacturers |
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6 / 15 page  (OLWH07 M11B11664A Elite Memory Technology Inc Publication Date : Dec. 2000 Revision : 1.3 6/15 Notes : 1. Enables on-chip refresh and address counters. 2. VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL. 3. In addition to meet the transition rate specification, all input signals must transit between VIH and VIL in a monotonic manner. 4. Assume that tRCD < tRCD(max). If tRCD is greater than the maximum recommended value shown in this table, tRAC will increase by the amount that tRCD exceeds the value shown. 5. Assume that tRCD ≥ tRCD (max) 6. If CAS is low at the falling edge of RAS , data-out will be maintained from the previous cycle. To initiate a new cycle and clear the data-out buffer, CAS and RAS must be pulsed high. 7. Operation within the tRCD limit ensures that tRCD (max) can be met, tRCD (max) is specified as a reference point only ; if tRCD is greater than the specified tRCD (max) limit, access time is controlled by tCAC. 8. Operation within the tRAD limit ensures that tRAD(max) can be met. tRAD(max) is specified as a reference point only ; if tRAD is greater than the specified tRAD (max) limit, access time is controlled by tAA. 9. Either tRCH or tRRH must be satisfied for a READ cycle. 10. tOFF1(max) defines the time at which the output achieves the open circuit condition ; it is not a reference to VOH or VOL. 11. tWCS, tRWD, tAWD and tCWD are restrictive operating parameters in LATE WRITE and READ-MODIFY- WRITE cycle only. If tWCS ≥ tWCS(min) , the cycle is an EARLY WRITE cycle and the data output will remain an open circuit throughout the entire cycle. If tRWD ≥ tRWD(min) , tAWD ≥ tAWD(min) and tCWD ≥ tCWD(min) , the cycle is READ-WRITE and the data output will contain data read from the selected cell. If neither of the above conditions is met, the state of I/O (at access time and until CAS and RAS or OE go back to VIH ) is indeterminate. OE held high and WE taken low after CAS goes low result in a LATE WRITE ( OE -controlled) cycle. 12. Those parameters are referenced to CAS leading edge in EARLY WRITE cycles and WE leading edge in LATE WRITE or READ-MODIFY- WRITE cycles. 13. During a READ cycle, if OE is low then taken HIGH before CAS goes high, I/O goes open, if OE is tied permanently low, a LATE WRITE or READ-MODIFY- WRITE operation is not possible. 14. An initial pause of 200 µ s is required after power-up followed by eight RAS refresh cycles ( RAS only or CBR) before proper device operation is assured. The eight RAS cycle wake-ups should be repeated any time the tREF refresh requirement is exceeded. 15. WRITE command is defined as WE going low. 16. LATE WRITE and READ-MODIFY-WRITE cycles must have both tOFF2 and tOEH met ( OE high during WRITE cycle) in order to ensure that the output buffers will be open during the WRITE cycles. 17. The I/Os open during READ cycles once tOFF1 or tOFF2 occur. 18. Referenced to the earlier CAS falling edge. 19. Referenced to the latter CAS rising edge. 20. Output parameter (I/O) is referenced to corresponding CAS input, IO0~7 by CASL and IO8~15 by CASH . 21. Last falling CAS edge to first rising CAS edge. 22. Last rising CAS edge to next cycle’s last rising CAS edge. 23. Last rising CAS edge to first falling CAS edge. 24. Each CAS must meet minimum pulse width. 25. Referenced to the latter CAS failing edge. 26. All IOs controlled by OE , regardless CASL and CASH . |
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