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OV6120 Datasheet(PDF) 6 Page - List of Unclassifed Manufacturers |
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OV6120 Datasheet(HTML) 6 Page - List of Unclassifed Manufacturers |
6 / 31 page OV6620/OV6120 6 Version 1.11 14 May 1999 SINGLE IC CMOS COLOR AND B/W DIGITAL CAMERAS OMNIVISION TECHNOLOGIES, Inc. Advanced Information Preliminary Figure 2. Zoom Video Port Timing Notes: 1. Zoom Video Port format output signal includes: VSYNC: Vertical sync pulse. HREF: Horizontal valid data output window. PCLK: Pixel clock used to clock valid data and CHSYNC into Zoom V Port. Default frequency is 8.86MHz when use 17.73MHz as system clock. Rising edge of PCLK is used to clock the 16 Bit data. Y[7:0]: 8 Bit luminance data bus. UV[7:0]: 8 Bit chrominance data bus. 2. All timing parameters are provided in Table 13. Zoom Video Port AC Parameters VSYNC PCLK Y[7:0] UV[7:0] / HREF 351 352 t8 t8 Even Field 1(FODD=0) Odd Field(FODD=1) t6 t7 t1 t2 t3 t4 Horizontal Timing VSYNC Y[7:0]/ UV[7:0] Valid Data 1 Line Tvs Tve t5 Tline 1 2 |
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