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PALCE26V12H-15PC Datasheet(PDF) 5 Page - Advanced Micro Devices |
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PALCE26V12H-15PC Datasheet(HTML) 5 Page - Advanced Micro Devices |
5 / 21 page AMD 2–310 PALCE26V12 Family The feedback multiplexer is controlled by the same bit (S1) that controls whether the output is registered or combinatorial, as on the 22V10, with an additional control bit (S3) that allows the alternative feedback path to be selected. When S3 = 1, S1 selects register feedback for registered outputs (S1 = 0) and I/O feedback for combinatorial outputs (S1 = 1). When S3 = 0, the opposite is selected: I/O feedback for registered outputs and register feedback for combinatorial outputs. Programmable Enable and I/O Each macrocell has a three-state output buffer con- trolled by an individual product term. Enable and disable can be a function of any combination of device inputs or feedback. The macrocell provides a bidirectional I/O pin if I/O feedback is selected, and may be configured as a dedicated input if the buffer is always disabled. This is accomplished by connecting all inputs to the enable term, forcing the AND of the complemented inputs to be always LOW. To permanently enable the outputs, all inputs are left disconnected from the term (the unprogrammed state). Programmable Output Polarity The polarity of each macrocell output can be active high or active low, either to match output signal needs or to reduce product terms. Programmable polarity allows Boolean expressions to be written in their most compact form (true or inverted), and the output can still be of the desired polarity. It can also save “DeMorganizing” efforts. Selection is controlled by programmable bit S0 in the output macrocell, and affects both registered and combinatorial outputs. Selection is automatic, based on the design specification and pin definitions. If the pin definition and output equation have the same polarity, the output is programmed to be active high. Preset/Reset For initialization, the PALCE26V12 has additional Preset and Reset product terms. These terms are connected to all registered outputs. When the Synchro- nous Preset (SP) product term is asserted high, the output registers will be loaded with a HIGH or the next LOW-to-HIGH clock transition. When the Asynchronous Reset (AR) product term is asserted high, the output registers will be immediately loaded with a LOW independent of the clock. Note that preset and reset control the flip-flop, not the output pin. The output level is determined by the output polarity selected. Power-Up Reset All flip-flops power up to a logic LOW for predictable system initialization. Outputs of the PALCE26V12 will be HIGH or LOW depending on whether the output is active low or active high, respectively. The VCC rise must be monotonic, and the reset delay time is 1000 ns maximum. Register Preload The register on the PALCE26V12 can be preloaded from the output pins to facilitate functional testing of complex state machine designs. This feature allows direct loading of arbitrary states, thereby making it unnecessary to cycle through long test vector se- quences to reach a desired state. In addition, transitions from illegal states can be verified by loading illegal states and observing proper recovery. Security Bit After programming and verification, a PALCE26V12 design can be secured by programming the security bit. Once programmed, this bit defeats readback of the internal programmed pattern by a device programmer, securing proprietary designs from competitors. Pro- gramming the security bit disables preload, and the array will read as if every bit is disconnected. The security bit can only be erased in conjunction with erasure of the entire pattern. Programming and Erasing The PALCE26V12 can be programmed on standard logic programmers. It also may be erased to reset a previously configured device back to its virgin state. Erasure is automatically performed by the programming hardware. No special erase operation is required. Quality and Testability The PALCE26V12 offers a very high level of built-in quality. The erasability of the device provides a means of verifying performance of all AC and DC parameters. In addition, this verifies complete programmability and functionality of the device to provide the highest programming yields and post-programming functional yields in the industry. Technology The high-speed PALCE26V12 is fabricated with AMD’s advanced electrically erasable (EE) CMOS process. The array connections are formed with proven EE cells. Inputs and outputs are designed to be compatible with TTL devices. This technology provides strong input clamp diodes, output slew-rate control, and a grounded substrate for clean switching. |
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