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PCI9080 Datasheet(PDF) 3 Page - List of Unclassifed Manufacturers |
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3 / 133 page TABLE OF CONTENTS © ©PLX Technology, Inc., 1997 Page iii Version 0.93 3. FUNCTIONAL DESCRIPTION................................................................................................................................... 10 3.1 RESET ................................................................................................................................................................. 10 3.1.1 PCI Bus Input RST# ....................................................................................................................................... 10 3.1.2 Local Bus Input LRESETi# ............................................................................................................................. 10 3.1.3 Local Bus Output LRESETo# ......................................................................................................................... 10 3.1.4 Software Reset............................................................................................................................................... 10 3.2 PCI 9080 INITIALIZATION.................................................................................................................................... 10 3.2.1 EEPROM Initialization..................................................................................................................................... 10 3.2.2 Local Initialization ........................................................................................................................................... 10 3.3 EEPROM.............................................................................................................................................................. 10 3.3.1 Short EEPROM Load ..................................................................................................................................... 11 3.3.2 Long EEPROM Load ...................................................................................................................................... 11 3.3.3 Extra Long EEPROM Load............................................................................................................................. 13 3.3.4 Recommended EEPROMs ............................................................................................................................. 13 3.4 INTERNAL REGISTER ACCESS ......................................................................................................................... 13 3.4.1 PCI Bus Access to Internal Registers ............................................................................................................. 13 3.4.2 Local Bus Access to Internal Registers ........................................................................................................... 14 3.5 DIRECT DATA TRANSFER MODES .................................................................................................................... 14 3.5.1 Direct Master Operation (Local Master to PCI Target)..................................................................................... 15 3.5.1.1 Decode ..................................................................................................................................................................... 15 3.5.1.2 FIFOs ....................................................................................................................................................................... 15 3.5.1.3 Memory Access ........................................................................................................................................................ 15 3.5.1.4 IO/CFG Access......................................................................................................................................................... 15 3.5.1.5 I/O ............................................................................................................................................................................ 16 3.5.1.6 CFG (PCI Configuration Type 0 or Type 1 Cycles) .................................................................................................... 16 3.5.1.7 Direct Bus Master Lock ............................................................................................................................................. 16 3.5.1.8 Master/Target Abort .................................................................................................................................................. 16 3.5.1.9 Write and Invalidate.................................................................................................................................................. 16 3.5.2 Direct Slave Operation (PCI Master to Local Bus Access) .............................................................................. 18 3.5.2.1 PCI to Local Address Mapping .................................................................................................................................. 18 3.5.2.1.1 Byte Enables...................................................................................................................................................... 18 3.5.2.1.2 Local Bus Initialization Software ......................................................................................................................... 19 3.5.2.1.3 PCI Initialization Software .................................................................................................................................. 19 3.5.2.2 Deadlock and BREQo ............................................................................................................................................... 21 3.5.2.2.1 Backoff .............................................................................................................................................................. 21 3.5.2.2.2 Software/Hardware Solution for Systems without Backoff Capability................................................................... 22 3.5.2.2.3 Software Solutions to Deadlock .......................................................................................................................... 22 |
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