TOSHIBA

TB62726AN, TB62726AF

Timing diagram

Warning :

Latch circuit is leveled-latch circuit. Be careful because it is not triggered-latch circuit.

Note 2 :

The latches circuit holds data by pulling the LATCH terminal Low. And, when LATCH terminal is a High-level, latch

circuit doesn’t hold data, and it passes from theInput to the output. When ENABLE terminal is Low-level, output

terminal OUT0~OUT15 respond to the data, and on & off does.

And, when ENABLE terminal is a High-level, it offs with the output terminal regardless of the data.

TB62726AN, TB62726AF (Ver.5) 2002, Nov. 20

th

page 3/16

CLOCK

SERIAL-IN

LATCH

ENABLE

OUT0

OUT1

OUT3

OUT15

SERIAL-OUT

3.3v/5v

0V

3.3v/5v

0V

3.3v/5v

0V

3.3v/5v

0V

On

Off

On

Off

On

Off

On

Off

3.3v/5v

0V

n=0 1 2 3 4 5 6 7 8 9 101112131415