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U63716DK70G1 Datasheet(PDF) 1 Page - List of Unclassifed Manufacturers |
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U63716DK70G1 Datasheet(HTML) 1 Page - List of Unclassifed Manufacturers |
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1 / 13 page  1 April 7, 2005 U63716 CapStore 2K x 8 nvSRAM Pin Configuration Pin Description Signal Name Signal Description A0 - A10 Address Inputs DQ0 - DQ7 Data In/Out E Chip Enable G Output Enable W Write Enable VCC Power Supply Voltage VSS Ground CMOS non- volatile static RAM 2048 x 8 bits 70 ns Access Time 35 ns Output Enable Access Time ICC = 15 mA at 200 ns Cycle Time Unlimited Read and Write Cycles to SRAM Automatic STORE to EEPROM on Power Down using charge stored in an integrated capacitor Software initiated STORE Automatic STORE Timing 106 STORE cycles to EEPROM 100 years data retention in EEPROM Automatic RECALL on Power Up Software RECALL Initiation Unlimited RECALL cycles from EEPROM Single 5 V ± 10 % Operation Operating temperature range: 0 to 70 °C -40 to 85 °C QS 9000 Quality Standard ESD protection > 2000 V (MIL STD 883C M3015.7) RoHS compliance and Pb- free Package: PDIP24 (600 mil) The U63716 has two separate modes of operation: SRAM mode and nonvolatile mode. In SRAM mode, the memory operates as an ordinary static RAM. In non-volatile operation, data is transferred in parallel from SRAM to EEPROM or from EEPROM to SRAM. In this mode SRAM functions are disab- led. The U63716 is a static RAM with a non-volatile electrically erasable PROM (EEPROM) element incor- porated in each static memory cell. The SRAM can be read and written an unlimited number of times, while independent nonvolatile data resi- des in EEPROM. Data transfers from the SRAM to the EEPROM (the STORE operation) take place automatically upon power down using charge stored in an integra- ted capacitor. Transfers from the EEPROM to the SRAM (the RECALL operation) take place automatically on power up. The U63716 combines the ease of use of an SRAM with nonvolatile data integrity. STORE cycles also may be initia- ted under user control via a soft- ware sequence. Once a STORE cycle is initiated, further input or output are disabled until the cycle is completed. Because a sequence of addresses is used for STORE initiation, it is important that no other read or write accesses intervene in the sequence or the sequence will be aborted. RECALL cycles may also be initia- ted by a software sequence. Internally, RECALL is a two step procedure. First, the SRAM data is cleared and second, the nonvola- tile information is transferred into the SRAM cells. The RECALL operation in no way alters the data in the EEPROM cells. The nonvolatile data can be recalled an unlimited number of times. The U63716 is pin compatible with standard SRAMs and standard bat- tery backed SRAMs. Top View 2 A6 A8 23 3 A5 A9 22 1 A7 VCC 24 4 A4 W 21 5 A3 G 20 6 A2 A10 19 10 DQ1 DQ5 15 7 A1 E 18 8 A0 DQ7 17 9 DQ0 DQ6 16 11 DQ2 DQ4 14 12 VSS DQ3 13 PDIP 24 Features Description |
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