U6264BS2A07 datasheet(1/9 Pages) ZMD

Part #	U6264BS2A07

Description	STANDARD 5K X 8 SRAM

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Manufacturer	ZMD [Zentrum Mikroelektronik Dresden AG]

Direct Link	http://www.zmdi.com

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April 20, 2004

U6264B

Standard 8K x 8 SRAM

The U6264B is a static RAM manu-

factured using a CMOS process

technology with the following ope-

rating modes:

- Read

- Standby

- Write

- Data Retention

The memory array is based on a

6-transistor cell.

The circuit is activated by the rising

edge of E2 (at E1 = L), or the falling

edge of E1 (at E2 = H). The

address and control inputs open

simultaneously. According to the

information of W and G, the data

inputs, or outputs, are active. In a

Read cycle, the data outputs are

activated by the falling edge of G,

afterwards the data word read will

be available at the outputs DQ0 -

DQ7. After the address change, the

data outputs go High-Z until the

new read information is available.

The data outputs have no preferred

state. If the memory is driven by

CMOS levels in the active state,

and if there is no change of the

address, data input and control

signals W or G, the operating cur-

rent (at IO = 0 mA) drops to the

value of the operating current in the

Standby mode. The Read cycle is

finished by the falling edge of E2 or

W, or by the rising edge of E1,

respectively.

Data retention is guaranteed down

to 2 V. With the exception of E2, all

inputs consist of NOR gates, so

that no pull-up/pull-down resistors

are required. This gate circuit

allows to achieve low power

standby requirements by activation

with TTL-levels too.

If the circuit is inactivated by

E2 = L, the standby current (TTL)

drops to 150

µA typ.

!

8192 x 8 bit static CMOS RAM

!

70 ns Access Times

!

Common data inputs and

outputs

!

Three-state outputs

!

Typ. operating supply current

70 ns: 10 mA

!

Standby current:

< 2

µA at Ta ≤ 70 °C

!

Data retention current at 2 V:

< 1

µA at Ta ≤ 70 °C

!

TTL/CMOS-compatible

!

Automatic reduction of power

dissipation in long Read or Write

cycles

!

Power supply voltage 5 V

!

Operating temperature ranges:

0 to 70

°C

-40 to 85

°C

-40 to 125 °C

!

QS 9000 Quality Standard

!

ESD protection > 2000 V

(MIL STD 883C M3015.7)

!

Latch-up immunity > 100 mA

!

Packages: PDIP28 (600 mil)

SOP28 (330 mil)

Pin Description

Signal Name

Signal Description

A0 - A12

Address Inputs

DQ0 - DQ7

Data In/Out

E1

Chip Enable 1

E2

Chip Enable 2

G

Output Enable

W

Write Enable

VCC

Power Supply Voltage

VSS

Ground

n.c.

not connected

Pin Configuration

1

n.c.

VCC

28

2

A12

W (WE)

27

4

A6

A8

25

5

A5

A9

24

3

A7

E2 (CE2)

26

6

A4

A11

23

7

A3

G (OE)

22

8

A2

A10

21

12

DQ1

DQ5

17

9

A1

E1 (CE1)

20

10

A0

DQ7

19

11

DQ0

DQ6

18

13

DQ2

DQ4

16

14

VSS

DQ3

15

PDIP

Top View

SOP

Features

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