ADP3166JRU-REEL7 datasheet(8/20 Pages) AD

Part #	ADP3166JRU-REEL7

Description	5-Bit Programmable 2-, 3-, 4-Phase Synchronous Buck Controller

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Manufacturer	AD [Analog Devices]

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REV. 0

–8–

ADP3166

This amplifier can be configured several ways depending on the

objectives of the system:

• Output inductor ESR sensing without thermistor for

lowest cost

• Output inductor ESR sensing with thermistor for improved

accuracy with tracking of inductor temperature

• Sense resistors for highest accuracy measurements

The positive input of the CSA is connected to the CSREF pin,

which is connected to the output voltage. The inputs to the

amplifier are summed together through resistors from the sensing

element (such as the switch node side of the output inductors) to

the inverting input, CSSUM. The feedback resistor between

CSCOMP and CSSUM sets the gain of the amplifier, and a filter

capacitor is placed in parallel with this resistor. The gain of the

amplifier is programmable by adjusting the feedback resistor to

set the load line required by the microprocessor. The current

information is then given as the difference of CSREF – CSCOMP.

This difference signal is used internally to offset the VID DAC

for voltage positioning, and as a differential input for the current

limit comparator.

To provide the best accuracy for the sensing of current, the

CSA has been designed to have a low offset input voltage. Also,

the sensing gain is determined by external resistors so that it can

be made extremely accurate.

Active Impedance Control Mode

For controlling the dynamic output voltage droop as a function

of output current, a signal proportional to the total output cur-

rent at the CSCOMP pin can be scaled to be equal to the droop

impedance of the regulator times the output current. This droop

voltage is then used to set the input control voltage to the sys-

tem. The droop voltage is subtracted from the DAC reference

input voltage directly to tell the error amplifier where the output

voltage should be. This differs from previous implementations

and allows enhanced feed-forward response.

Voltage Control Mode

A high gain-bandwidth voltage mode error amplifier is used for

the voltage mode control loop. The control input voltage to the

positive input is set via the VID 5-bit logic code according to

the voltages listed in Table I. This voltage is also offset by the

droop voltage for active positioning of the output voltage as a

function of current, commonly known as active voltage position-

ing. The output of the amplifier is the COMP pin, which sets

the termination voltage for the internal PWM ramps.

The negative input (FB) is tied to the output sense location with

a resistor, RB, and is used for sensing and controlling the output

voltage at this point. A current source from the FB pin flowing

through RB is used for setting the no-load offset voltage from

the VID voltage. The no-load voltage will be positive with respect

to the VID DAC. The main loop compensation is incorporated

in the feedback network between FB and COMP.

Soft Start

The power-on ramp-up time of the output voltage is set with a

capacitor and resistor in parallel from the DELAY pin to ground.

The RC time constant also determines the current limit latch-off

time, as explained in the following section. In UVLO or when

EN is a logic low, the DELAY pin is held at ground. After the

UVLO threshold is reached and EN is a logic high, the DELAY

capacitor is charged up with an internal 20

µA current source.

The output voltage follows the ramping voltage on the DELAY

pin, limiting the inrush current. The soft start time depends on

the value of VID DAC and CDLY, with a secondary effect from

RDLY. Refer to the Applications section for detailed information

on setting CDLY.

When the PWRGD threshold is reached, the soft start cycle is

stopped and the DELAY pin is pulled up to 3 V. This ensures

that the output voltage is at the VID voltage when the PWRGD

signals to the system that the output voltage is good. If EN is

taken low or if VCC drops below UVLO, the DELAY capacitor

is reset to ground to be ready for another soft start cycle.

Current Limit and Short-Circuit Protection

The ADP3166 compares a programmable current limit set point

to the voltage on the output of the current sense amplifier at the

CSCOMP pin. The level of current limit is set with the resistor

from the ILIMIT pin to ground. During normal operation, the

voltage on ILIMIT is 3 V. The current through the external

resistor is internally scaled to give a current limit threshold of

10.4 mV/

µA. If the difference in voltage between CSREF and

CSCOMP drops below the current limit threshold, the internal

current limit amplifier will control the internal COMP voltage

to maintain the average output current at the limit.

After the limit is reached, the 3 V pull-up on the DELAY pin is

disconnected, and the external delay capacitor is discharged

through the external resistor. A comparator monitors the DELAY

voltage and shuts off the controller when the voltage drops

below 1.8 V. The current limit latch-off delay time is therefore

set by the RC time constant discharging from 3 V to 1.8 V. The

Applications section discusses the selection of RDLY based on

the CDLY that has been chosen.

Because the controller continues to cycle the phases during the

latch-off delay time, if the short is removed before the 1.8 V

threshold is reached, the controller will return to normal operation.

The recovery characteristic depends on the state of PWRGD. If

the output voltage is within the PWRGD window, the controller

resumes normal operation. However, if short circuit has caused

the output voltage to drop below the PWRGD threshold, then a

soft start cycle is initiated.

The latch-off function can be reset by either removing and

reapplying VCC to the ADP3166, or by pulling the EN pin low

for a short time. To disable the short-circuit latch-off function,

the external resistor to ground should be left open, and a large

(greater than 1 M

Ω) resistor should be connected from VCC to

DELAY. This prevents the DELAY capacitor from discharging

so the 1.8 V threshold is never reached. The resistor will have

an impact on the soft start time because the current through it

will add to the internal 20

µA current source.

During startup when the output voltage is below 200 mV, a

secondary current limit is active. This is necessary because the

voltage swing of CSCOMP cannot go below ground. This sec-

ondary current limit controls the internal COMP voltage to the

PWM comparators to 2 V. This will limit the voltage drop across

the low-side MOSFETs through the current balance circuitry.

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ADP3166JRU-REEL7 Datasheet(PDF) 8 Page - Analog Devices

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