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ASM690 Datasheet(PDF) 3 Page - Alliance Semiconductor Corporation |
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ASM690 Datasheet(HTML) 3 Page - Alliance Semiconductor Corporation |
3 / 13 page 3 of 13 Notice: The information in this document is subject to change without notice ASM690A / 692A ASM802L / 802M ASM805L µP Power Supply Supervisor With Battery Backup Switch rev 1.0 October 2003 Detailed Description It is important to initialize a microprocessor to a known state in response to specific events that could create code execution errors and “lock-up”. The reset output of these supervisory circuits send a reset pulse to the microprocessor in response to power-up, power-down/power-loss or a watchdog time-out. RESET/RESET Timing Power-up reset occurs when a rising VCC reaches the reset threshold, VRT, forcing a reset condition in which the reset output is asserted in the appropriate logic state for the duration of tRS. The reset pulse width, tRS, is typically around 200ms and is LOW for the ASM690A, ASM692A, ASM802 and HIGH for the ASM805L. Figure 1 shows the reset pin timing. Power-loss or “brown-out” reset occurs when VCC dips below the reset threshold resulting in a reset assertion for the duration of tRS. The reset signal remains asserted as long as VCC is between VRT and 1.1V, the lowest VCC for which these devices can provide a guaranteed logic-low output. To ensure logic inputs connected to the ASM690A / ASM692A/ASM802 RESET pin are in a known state when VCC is under 1.1V, a 100k Ω pull-down resistor at RESET is needed: the logic-high ASM805L will need a pull-up resistor to VCC. Watchdog Timer A Watchdog time-out reset occurs when a logic “1” or logic “0” is continuously applied to the WDI pin for more than 1.6 seconds. After the duration of the reset interval, the watchdog timer starts a new 1.6 second timing interval; the microprocessor must service the watchdog input by changing states or by floating the WDI pin before this interval is finished. If the WDI pin is held either HIGH or LOW, a reset pulse will be triggered every 1.8 seconds (the 1.6 second timing interval plus the reset pulse width tRS). Application Information Microprocessor Interface The ASM690 has logic-LOW RESET output while the ASM805 has an inverted logic-HIGH RESET output. Microprocessors with bidirectional reset pins can pose a problem when the supervisory circuit and the microprocessor output pins attempt to go to opposite logic states. The problem can be resolved by placing a 4.7k Ω resistor between the RESET output and the microprocessor reset pin. This is shown in Figure 2. Since the series resistor limits drive capabilities, the reset signal to other devices should be buffered. Figure 1: RESET/RESET Timing Figure 2: Interfacing with bi-directional microprocessor reset inputs VCC RESET RESET GND GND VCC ASM690A Power Supply Bi-directional I/O pin RESET Buffered BUF 4.7K Ω |
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