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L5510 Datasheet(PDF) 2 Page - STMicroelectronics |
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L5510 Datasheet(HTML) 2 Page - STMicroelectronics |
2 / 3 page L5510 2/3 7 Other Features ■ 208-pin QFP package ■ Automatic and programmed power-down modes ■ 3.3 V I/Os with 5 V tolerance, 2.5 V logic core ■ Programmable read channel and preamp VCM serial interfaces ■ Dual on-chip frequency synthesizers optimize DSP, servo, Ultra-DMA and buffer performance ■ General purpose I/O and PWM pins ■ Programmable baud-rate RS232 interface 8 DESCRIPTION The Device is a highly integrated, automated sin- gle-chip Drive Manager and Disk Drive Controller IC designed for high-performance, headerless ATA drive applications. Figure 2 shows the chip’s main functional blocks. Figure 2. Functional Block Diagram Table 2. Revision History Date Revision Description of Changes December 2004 1 First Issue DCTL HIF BCTL EDAC SERVO DSP SRAM FLASH BUFFER SDRAM READ CHANNEL ATA BUS ROM ROM RAM PERIPHERALS (SYNC or ASYNC) |
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