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IDT70914S12FB Datasheet(PDF) 7 Page - Integrated Device Technology |
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IDT70914S12FB Datasheet(HTML) 7 Page - Integrated Device Technology |
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7 / 11 page  6.42 IDT70914S High-Speed 36K (4K x 9) Synchronous Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges 7 AC Electrical Characteristics Over the Operating Temperature Range (Read and Write Cycle Timing)(3) (Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Military: VCC = 5V ± 10%, TA = -55°C to +125°C) NOTES: 1. Transition is measured 0mV from Low or High impedance voltage with the Output Test Load (Figure 2). 2. This parameter is guaranteed by device characterization, but is not production tested. 3. Industrial temperature: for specific speeds, packages and powers contact your sales office. 70914S12 Com'l Only 70914S15 Com'l Only Symbol Param eter Min. Max. Min. Max. Unit tCYC Clock Cycle Time 16 ____ 20 ____ ns tCH Clock High Time 6 ____ 6 ____ ns tCL Clock Low Time 6 ____ 6 ____ ns tCD Clock High to Output Valid ____ 12 ____ 15 ns tS Registered Signal Set-up Time 4 ____ 4 ____ ns tH Registered Signal Hold Time 1 ____ 1 ____ ns tDC Data Output Hold After Clock High 3 ____ 3 ____ ns tCKLZ Clock High to Output Low-Z(1,2) 2 ____ 2 ____ ns tCKHZ Clock High to Output High-Z (1,2) ____ 7 ____ 7ns tOE Output Enable to Output Valid ____ 7 ____ 8ns tOLZ Output Enable to Output Low-Z (1,2) 0 ____ 0 ____ ns tOHZ Output Disable to Output High-Z(1,2) ____ 7 ____ 7ns tSCK Clock Enable, Disable Set-up Time 4 ____ 4 ____ ns tHCK Clock Enable, Disable Hold Time 2 ____ 2 ____ ns Port-to-Port Delay tCWDD Write Port Clock Hig h to Read Data Delay ____ 25 ____ 30 ns tCSS Clock-to-Clock Setup Time ____ 13 ____ 15 ns 3490 tbl 08a 70914S20 Com'l & Military 70914S25 Military Only Symbol Param eter Min. Max. Min. Max. Unit tCYC Clo c k Cy cle Time 20 ____ 25 ____ ns tCH Cloc k High Time 8 ____ 10 ____ ns tCL Clo c k Lo w Time 8 ____ 10 ____ ns tCD Cloc k High to Outp ut Valid ____ 20 ____ 25 ns tS Re gis tered S ig nal S e t-up Time 5 ____ 6 ____ ns tH Re gis tered S ig nal Ho ld Time 1 ____ 1 ____ ns tDC Data Outp ut Ho ld A fte r Clo ck Hig h 3 ____ 3 ____ ns tCKLZ Cloc k High to Outp ut Lo w-Z (1,2) 2 ____ 2 ____ ns tCKHZ Clo c k Hig h to Outp ut Hig h-Z (1,2) ____ 9 ____ 12 ns tOE Outp ut E nab le to Outp ut Valid ____ 10 ____ 12 ns tOLZ Outp ut E nab le to Outp ut Lo w-Z (1,2) 0 ____ 0 ____ ns tOHZ Outp ut Dis ab le to Outp ut Hig h-Z (1,2) ____ 9 ____ 11 ns tSCK Cloc k E nab le , Disable S e t-up Time 5 ____ 6 ____ ns tHCK Clo c k E nab le , Disab le Ho ld Time 2 ____ 2 ____ ns Port-to-Port Delay tCWDD W rite P o rt Clo ck Hig h to Re ad Data De lay ____ 35 ____ 45 ns tCSS Clo c k-to -Clo ck S e tup Tim e ____ 15 ____ 20 ns 3490 tbl 08b |
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