HMS30C7210 datasheet(6/337 Pages) ETC

Part #	HMS30C7210

Description	ARM Based 32-Bit Microprocessor

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Contents

MagnaChip Semiconductor Ltd.

HMS30C7210 DataSheet (DS-07)

ii

7.1

SUPPORTED MEMORY DEVICES ...................................................................................- 60 -

7.2

EXTERNAL SIGNALS ...................................................................................................- 61 -

7.3

REGISTERS .................................................................................................................- 61 -

7.3.1

SDRAM Controller Configuration Register (SDCON)...........................................- 62 -

7.3.2

SDRAM Controller Refresh Timer Register (SDREF)............................................- 64 -

7.3.3

SDRAM Controller Write buffer flush timer Register (SDWBF) ............................- 64 -

7.4

POWER-UP INITIALIZATION OF THE SDRAMS..............................................................- 65 -

7.5

SDRAM MEMORY MAP .............................................................................................- 66 -

7.6

AMBAACCESSES AND ARBITRATION .........................................................................- 69 -

7.7

MERGING WRITE BUFFER ...........................................................................................- 70 -

8

STATIC MEMORY INTERFACE............................................................................- 73 -

8.1

EXTERNAL SIGNALS ...................................................................................................- 74 -

8.2

REGISTERS .................................................................................................................- 74 -

8.2.1

MEM Configuration Register.................................................................................- 75 -

8.3

FUNCTIONAL DESCRIPTION.........................................................................................- 76 -

8.3.1

Memory bank select ...............................................................................................- 76 -

8.3.2

Access sequencing..................................................................................................- 76 -

8.3.3

Wait states generation ............................................................................................- 76 -

8.3.4

Burst read control ..................................................................................................- 76 -

8.3.5

Byte lane write control ...........................................................................................- 77 -

8.4

READ, WRITE TIMING DIAGRAM FOR EXTERNAL MEMORY .........................................- 80 -

8.4.1

Read Access Timing (Single mode).........................................................................- 80 -

8.4.2

Read Access Timing (Burst mode).......................................................................- 81 -

8.4.3

Write Access Timing ...............................................................................................- 82 -

9

AMBA PERIPHERALS ............................................................................................- 83 -

9.1

LCD CONTROLLER................................................................................................- 85 -

9.1.1

External Signals .....................................................................................................- 86 -

9.1.2

Registers.................................................................................................................- 86 -

9.1.3

LCD controller datapath........................................................................................- 94 -

9.1.4

Color/Grayscale dithering .....................................................................................- 95 -

9.1.5

LCD panel dependent settings................................................................................- 96 -

9.1.6

Frame data dependent settings ............................................................................- 103 -

9.1.7

Other settings.......................................................................................................- 105 -

9.2

INTERRUPT CONTROLLER .........................................................................................- 107 -

9.2.1

Registers...............................................................................................................- 108 -

9.2.2

Interrupt Control.................................................................................................. - 111 -

9.3

USB SLAVE INTERFACE ............................................................................................ - 113 -

9.3.1

Block Diagram .....................................................................................................- 114 -

9.3.2

External Signals ...................................................................................................- 115 -

9.3.3

Registers...............................................................................................................- 115 -

9.3.4

Theory of Operation.............................................................................................- 122 -

9.3.5

Endpoint FIFOs (Rx, Tx)......................................................................................- 125 -

9.4

ADC INTERFACE CONTROLLER.................................................................................- 127 -

9.4.1

External Signals ...................................................................................................- 128 -

9.4.2

Registers...............................................................................................................- 128 -

9.4.3

Operation .............................................................................................................- 136 -

9.4.4

A/D Converter......................................................................................................- 142 -

9.5

UART/SIR...............................................................................................................- 145 -

9.5.1

External Signals ...................................................................................................- 146 -

9.5.2

Registers...............................................................................................................- 147 -

9.5.3

FIFO Interrupt Mode Operation..........................................................................- 158 -

9.5.4

FIFO Polling Mode Operation ............................................................................- 159 -

9.6

SMART CARD INTERFACE .......................................................................................- 161 -

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