Dual, Ultra-Low-Power,

12-Bit, Voltage-Output DACs

6

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Note 1: Linearity is tested within codes 96 to 4080.

Note 2: Offset is tested at code 96.

Note 3: Gain is tested at code 4095. For the MAX5534/MAX5535, FB_ is connected to its respective OUT_.

Note 4: Guaranteed by design. Not production tested.

Note 7: Optimal noise performance is at 2nF load capacitance.

TIMING CHARACTERISTICS

(VDD = +1.8V to +5.5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Serial Clock Frequency

010

MHz

DIN to SCLK Rise Setup Time

24

ns

DIN to SCLK Rise Hold Time

0ns

SCLK Pulse-Width High

40

ns

SCLK Pulse-Width Low

40

ns

CS Pulse-Width High

150

ns

SCLK Rise to

CS Rise Hold Time

0ns

CS Fall to SCLK Rise Setup Time

30

ns

SCLK Fall to

CS Fall Setup

0ns

CS Rise to SCK Rise Hold Time

30

ns