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MAX5535ETC Datasheet(PDF) 6 Page - Maxim Integrated Products |
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MAX5535ETC Datasheet(HTML) 6 Page - Maxim Integrated Products |
6 / 24 page Dual, Ultra-Low-Power, 12-Bit, Voltage-Output DACs 6 _______________________________________________________________________________________ Note 1: Linearity is tested within codes 96 to 4080. Note 2: Offset is tested at code 96. Note 3: Gain is tested at code 4095. For the MAX5534/MAX5535, FB_ is connected to its respective OUT_. Note 4: Guaranteed by design. Not production tested. Note 5: VDD must be a minimum of 1.8V. Note 6: Outputs can be shorted to VDD or GND indefinitely, provided that package power dissipation is not exceeded. Note 7: Optimal noise performance is at 2nF load capacitance. Note 8: Thermal hysteresis is defined as the change in the initial +25°C output voltage after cycling the device from TMAX to TMIN. Note 9: All digital inputs at VDD or GND. Note 10: Load = 10kΩ in parallel with 100pF, VDD = 5V, VREF = 4.096V (MAX5532/MAX5534) or VREF = 3.9V (MAX5533/MAX5535). TIMING CHARACTERISTICS (VDD = +1.8V to +5.5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS TIMING CHARACTERISTICS (VDD = 1.8V to 5.5V ) Serial Clock Frequency fSCLK 010 MHz DIN to SCLK Rise Setup Time tDS 24 ns DIN to SCLK Rise Hold Time tDH 0ns SCLK Pulse-Width High tCH 40 ns SCLK Pulse-Width Low tCL 40 ns CS Pulse-Width High tCSW 150 ns SCLK Rise to CS Rise Hold Time tCSH 0ns CS Fall to SCLK Rise Setup Time tCSS 30 ns SCLK Fall to CS Fall Setup tCSO 0ns CS Rise to SCK Rise Hold Time tCS1 30 ns |
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