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DS26528 Datasheet(PDF) 4 Page - Maxim Integrated Products |
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DS26528 Datasheet(HTML) 4 Page - Maxim Integrated Products |
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4 / 269 page  DS26528 Octal T1/E1/J1 Transceiver 4 of 269 LIST OF FIGURES Figure 7-1. Block Diagram ..................................................................................................................... 15 Figure 7-2. Detailed Block Diagram ....................................................................................................... 16 Figure 8-1. BGA Pinout ......................................................................................................................... 23 Figure 9-1. Backplane Clock Generation ............................................................................................... 25 Figure 9-2. Device Interrupt Information Flow Diagram.......................................................................... 29 Figure 9-3. IBO Multiplexer Equivalent Circuit—4.096MHz.................................................................... 34 Figure 9-4. IBO Multiplexer Equivalent Circuit—8.192MHz.................................................................... 35 Figure 9-5. IBO Multiplexer Equivalent Circuit—16.384MHz.................................................................. 36 Figure 9-6. RSYNC Input In H.100 (Ct-Bus) Mode ................................................................................ 40 Figure 9-7. TSSYNCIO(Input Mode) Input In H.100 (CT-Bus) Mode...................................................... 41 Figure 9-8. CRC-4 Recalculate Method ................................................................................................. 63 Figure 9-9. Receive HDLC Example...................................................................................................... 69 Figure 9-10. HDLC Message Transmit Example.................................................................................... 71 Figure 9-11. Basic Balanced Network Connections ............................................................................... 73 Figure 9-12. Recommended Supply Decoupling.................................................................................... 75 Figure 9-13. T1/J1 Transmit Pulse Templates ....................................................................................... 77 Figure 9-14. E1 Transmit Pulse Templates............................................................................................ 78 Figure 9-15. Typical Monitor Application................................................................................................ 80 Figure 9-16. Jitter Attenuation ............................................................................................................... 83 Figure 9-17. Analog Loopback............................................................................................................... 83 Figure 9-18. Local Loopback ................................................................................................................. 84 Figure 9-19. Remote Loopback ............................................................................................................. 84 Figure 9-20. Dual Loopback .................................................................................................................. 85 Figure 10-1. Register Memory Map for the DS26528............................................................................. 89 Figure 11-1. T1 Receive Side D4 Timing ............................................................................................. 231 Figure 11-2. T1 Receive Side ESF Timing........................................................................................... 231 Figure 11-3. T1 Receive Side Boundary Timing (elastic store disabled) .............................................. 232 Figure 11-4. T1 Receive Side 1.544MHz Boundary Timing (e-store enabled)...................................... 232 Figure 11-5. T1 Receive Side 2.048MHz Boundary Timing (e-store enabled)...................................... 233 Figure 11-6. T1 Receive Side Interleave Bus Operation, BYTE Mode ................................................. 234 Figure 11-7. T1 Receive Side Interleave Bus Operation, FRAME Mode .............................................. 235 Figure 11-8. T1 Transmit Side D4 Timing ............................................................................................ 236 Figure 11-9. T1 Transmit Side ESF Timing.......................................................................................... 236 Figure 11-10. T1 Transmit Side Boundary Timing (e-store disabled) ................................................... 237 Figure 11-11. T1 Transmit Side 1.544MHz Boundary Timing (e-store enabled)................................... 237 Figure 11-12. T1 Transmit Side 2.048MHz Boundary Timing (e-store enabled)................................... 238 Figure 11-13. T1 Transmit Side Interleave Bus Operation, BYTE Mode .............................................. 239 Figure 11-14. T1 Transmit Interleave Bus Operation, FRAME Mode ................................................... 240 Figure 11-15. E1 Receive Side Timing ................................................................................................ 241 Figure 11-16. E1 Receive Side Boundary Timing (elastic store disabled) ............................................ 241 Figure 11-17. E1 Receive Side 1.544MHz Boundary Timing (e-store enabled) ................................... 242 Figure 11-18. E1 Receive Side 2.048MHz Boundary Timing (e-store enabled) ................................... 242 Figure 11-19. E1 Transmit Side Timing ............................................................................................... 243 Figure 11-20. E1 Transmit Side Boundary Timing (elastic store disabled) ........................................... 243 Figure 11-21. E1 Transmit Side 1.544MHz Boundary Timing (e-store enabled) .................................. 244 Figure 11-22. E1 Transmit Side 2.048MHz Boundary Timing (e-store enabled) .................................. 244 Figure 11-23. E1 G.802 Timing ........................................................................................................... 245 Figure 13-1. Intel Bus Read Timing (BTS = 0) ..................................................................................... 249 Figure 13-2. Intel Bus Write Timing (BTS = 0) ..................................................................................... 249 Figure 13-3. Motorola Bus Read Timing (BTS = 1) .............................................................................. 250 Figure 13-4. Motorola Bus Write Timing (BTS = 1) .............................................................................. 250 |
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Similar Description - DS26528 |
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