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MAX5033DASA Datasheet(PDF) 11 Page - Maxim Integrated Products |
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MAX5033DASA Datasheet(HTML) 11 Page - Maxim Integrated Products |
11 / 17 page 500mA, 76V, High-Efficiency, MAXPower Step-Down DC-DC Converter ______________________________________________________________________________________ 11 Ensure that the ripple specification of the input capaci- tor exceeds the worst-case capacitor RMS ripple cur- rent. Use the following equations to calculate the input capacitor RMS current: IPRMS is the input switch RMS current, IAVGIN is the input average current, and η is the converter efficiency. The ESR of aluminum electrolytic capacitors increases significantly at cold temperatures. Use a 1µF or greater value ceramic capacitor in parallel with the aluminum electrolytic input capacitor, especially for input voltages below 8V. Output Filter Capacitor The worst-case peak-to-peak and RMS capacitor ripple current, allowable peak-to-peak output ripple voltage, and the maximum deviation of the output voltage dur- ing load steps determine the capacitance and the ESR requirements for the output capacitors. The output capacitance and its ESR form a zero, which improves the closed-loop stability of the buck regulator. Choose the output capacitor so the ESR zero frequency (fZ) occurs between 20kHz to 40kHz. Use the following equation to verify the value of fZ. Capacitors with 100m Ω to 250m Ω ESR are recommended to ensure the closed- loop stability while keeping the output ripple low. The output ripple is comprised of ∆VOQ (caused by the capacitor discharge) and ∆VOESR (caused by the ESR of the capacitor). Use low-ESR tantalum or aluminum electrolytic capacitors at the output. Assuming that the contributions from the ESR and capacitor discharge equal 80% and 20%, respectively, calculate the output capacitance and the ESR required for a specified rip- ple using the following equations: The MAX5033 has an internal soft-start time (tSS) of 400µs. It is important to keep the output rise time at startup below tSS to avoid output overshoot. The output rise time is directly proportional to the output capacitor. Use 68µF or lower capacitance at the output to control the overshoot below 5%. In a dynamic load application, the allowable deviation of the output voltage during the fast-transient load dic- tates the output capacitance value and the ESR. The output capacitors supply the step load current until the controller responds with a greater duty cycle. The response time (tRESPONSE) depends on the closed- loop bandwidth of the converter. The resistive drop across the capacitor ESR and capacitor discharge cause a voltage droop during a step load. Use a com- bination of low-ESR tantalum and ceramic capacitors for better transient load and ripple/noise performance. Keep the maximum output-voltage deviation above the tolerable limits of the electronics being powered. Assuming a 50% contribution from the output capaci- tance discharge and the ESR drop, use the following equations to calculate the required ESR and capaci- tance value: where ISTEP is the load step and tRESPONSE is the response time of the controller. Controller response time is approximately one-third of the reciprocal of the closed-loop unity-gain bandwidth, 20kHz (typ). PC Board Layout Considerations Proper PC board layout is essential. Minimize ground noise by connecting the anode of the Schottky rectifier, the input bypass-capacitor ground lead, and the output filter-capacitor ground lead to a single point (star- C It V OUT STEP RESPONSE OQ = × ∆ ESR V I OUT OESR STEP = ∆ C I Vf OUT L OQ SW ≈ ×× ∆ ∆ 22 . ESR V I OUT OESR L = ∆ ∆ f C ESR Z OUT OUT = ×× × 1 2 π II I I I D I VI V II I II I and D V V PRMS PK DC PK DC AVGIN OUT OUT IN PK OUT L DC OUT L OUT IN =+ + × () × = × × =+ = − = 22 3 22 , η ∆∆ II I where CRMS PRMS AVGIN =− 22 |
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