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MIC2592B-5BTQ Datasheet(PDF) 9 Page - Micrel Semiconductor

Part # MIC2592B-5BTQ
Description  Dual-Slot PCI Express Hot-Plug Controller
Download  31 Pages
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Manufacturer  MICREL [Micrel Semiconductor]
Direct Link  http://www.micrel.com
Logo MICREL - Micrel Semiconductor

MIC2592B-5BTQ Datasheet(HTML) 9 Page - Micrel Semiconductor

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March 2005
9
M9999-033105
MIC2592B
Micrel
Electrical Characteristics (continued)(7)
Symbol
Parameter
Condition
Min
Typ
Max Units
IAUX(THRESH)
Auxiliary Output Current Limit
Current which must be drawn from
0.84
A
Threshold (Figure 4)
V
AUX(THRESH)
AUX(THRESH)
AUX
Threshold (Figure 4)
V
Threshold (Figure 4)
V
to register as a fault
ISC(TRAN)
Maximum Transient Short Circuit
VAUX
Maximum Transient Short Circuit
V
Maximum Transient Short Circuit
V
Enabled, then Grounded
Current
I
V
R
MAX
STBY[A/B]
DS(AUX)
A
ILIM(AUX)
Regulated Current after Transient
From end of ISC(TRAN) to CFILTER time-out 0.375
0.7
1.35
A
Output Discharge Resistance
RDIS(12V)
12VOUT[A/B]
12VOUT[A/B] = 6.0V
1600
Ω
RDIS(3V)
3VOUT[A/B]
3V
DIS(12V)
DIS(12V)
OUT[A/B] = 1.65V
150
Ω
RDIS(VAUX)
3VAUX[A/B]
3VAUX[A/B]
3VAUX[A/B]
3V
3VAUX[A/B]
3V
= 1.65V
430
Ω
tOFF(12V)
12V Current Limit Response Time
MIC2592B-2BTQ
1
2.0
µs
(Figure 2)
C
OFF(12V)
OFF(12V)
GATE = 25pF
VIN –VSENSE = 140mV
tOFF(3V)
3.3V Current Limit Response Time
MIC2592B-2BTQ
1
2.0
µs
(Figure 3)
C
OFF(3V)
OFF(3V)
GATE = 25pF
VIN –VSENSE = 140mV(8)
tSC(TRAN)
VAUX[A/B] Current Limit Response
VAUX[A/B]
VAUX[A/B] Current Limit Response
V
VAUX[A/B] Current Limit Response
V
= 0V, VSTBYA = V
STBYA
STBYA
STBYB = +3.3V
2.5
5
µs
Time (Figure 5)
SC(TRAN)
SC(TRAN)
tPROP(12VFAULT)
Delay from 12V[A/B] Overcurrent
MIC2592B-2BTQ
1
µs
Limit to /FAULT output
C
PROP(12VFAULT)
PROP(12VFAULT)
FILTER = 0
VIN –VSENSE = 140mV(8)
tPROP(3VFAULT)
Delay from 3V[A/B] Overcurrent
MIC2592B-2BTQ
1
µs
Limit to /FAULT[A/B] Output
C
PROP(3VFAULT)
PROP(3VFAULT)
FILTER = 0
VIN –VSENSE = 140mV(8)
tPROP(VAUXFAULT)
Delay from VAUX[A/B] Overcurrent
MIC2592B-2BTQ
1
µs
limit to /FAULT[A/B] output
PROP(VAUXFAULT)
PROP(VAUXFAULT)
CFILTER = 0
VAUX
V
V
Output Grounded(8)
tW
ON[A/B], AUXEN[A/B] Pulse Width
Note 8
100
ns
tPOR
MIC2592B Power-On Reset Time
Note 8
250
µs
after VSTBY[A/B] becomes valid
SMBus Timing
t1
SCL (clock) period
Figure 1
2.5
µs
t2
Data In setup time to SCL HIGH
Figure 1
100
ns
t3
Data Out stable after SCL LOW
Figure 1
300
ns
t4
Data LOW setup time to SCL LOW
Start condition, Figure 1
100
ns
t5
Data HIGH hold time after SCL HIGH Stop condition, Figure 1
100
ns
Notes:
7.
Specification for packaged product only.
8.
Parameters guaranteed by design. Not 100% production tested.
Symbol
Parameter
Condition
Min
Typ
Max Units
Auxiliary Output Current Limit
Current which must be drawn from
0.84
A
Threshold (Figure 4)
V
Maximum Transient Short Circuit
V
Current
Regulated Current after Transient
From end of I
Output Discharge Resistance
12VOUT[A/B]
12V
3VOUT[A/B]
3V
3VAUX[A/B]
3V
12V Current Limit Response Time
MIC2592B-2BTQ
1
(Figure 2)
C
V
3.3V Current Limit Response Time
MIC2592B-2BTQ
1
(Figure 3)
C
V
VAUX[A/B] Current Limit Response
V
Time (Figure 5)
Delay from 12V[A/B] Overcurrent
MIC2592B-2BTQ
1
µs
Limit to /FAULT output
C
V
Delay from 3V[A/B] Overcurrent
MIC2592B-2BTQ
1
µs
Limit to /FAULT[A/B] Output
C
V
Delay from VAUX[A/B] Overcurrent
MIC2592B-2BTQ
1
µs
limit to /FAULT[A/B] output
C
V
ON[A/B], AUXEN[A/B] Pulse Width
after VSTBY[A/B] becomes valid
Symbol
Parameter
Condition
Min
Typ
Max Units
Auxiliary Output Current Limit
Current which must be drawn from
0.84
A
Threshold (Figure 4)
V
Maximum Transient Short Circuit
V
Current
Regulated Current after Transient
From end of I
12VOUT[A/B]
12V
3VOUT[A/B]
3V
3VAUX[A/B]
3V
12V Current Limit Response Time
MIC2592B-2BTQ
1
(Figure 2)
C
V
3.3V Current Limit Response Time
MIC2592B-2BTQ
1
(Figure 3)
C
V
VAUX[A/B] Current Limit Response
V
Delay from 12V[A/B] Overcurrent
MIC2592B-2BTQ
1
µs
Limit to /FAULT output
C
V
Delay from 3V[A/B] Overcurrent
MIC2592B-2BTQ
1
µs
Limit to /FAULT[A/B] Output
C
V
Delay from VAUX[A/B] Overcurrent
MIC2592B-2BTQ
1
µs
limit to /FAULT[A/B] output
C
V
Symbol
Parameter
Condition
Min
Typ
Max Units
Auxiliary Output Current Limit
Current which must be drawn from
0.84
A
time-out
0.375
0.7
1.35
A
= 6.0V
1600
Ω
= 1.65V
150
Ω
= 1.65V
430
Ω
12V Current Limit Response Time
MIC2592B-2BTQ
1
3.3V Current Limit Response Time
MIC2592B-2BTQ
1
= +3.3V
2.5
Delay from 12V[A/B] Overcurrent
MIC2592B-2BTQ
1
µs
Delay from 3V[A/B] Overcurrent
MIC2592B-2BTQ
1
µs
Delay from VAUX[A/B] Overcurrent
MIC2592B-2BTQ
1
µs
Note 8
250
µs
time-out
0.375
0.7
1.35
A
= 6.0V
1600
Ω
= 1.65V
150
Ω
= 1.65V
430
Ω
12V Current Limit Response Time
MIC2592B-2BTQ
1
3.3V Current Limit Response Time
MIC2592B-2BTQ
1
= +3.3V
2.5
Delay from 12V[A/B] Overcurrent
MIC2592B-2BTQ
1
µs
Delay from 3V[A/B] Overcurrent
MIC2592B-2BTQ
1
µs
Delay from VAUX[A/B] Overcurrent
MIC2592B-2BTQ
1
µs
250
µs
time-out
0.375
0.7
1.35
A
= 6.0V
1600
Ω
= 1.65V
150
Ω
= 1.65V
430
Ω
Delay from 12V[A/B] Overcurrent
MIC2592B-2BTQ
1
µs
Delay from 3V[A/B] Overcurrent
MIC2592B-2BTQ
1
µs
Delay from VAUX[A/B] Overcurrent
MIC2592B-2BTQ
1
µs
250
µs
Symbol
Parameter
Condition
Min
Typ
Max Units
Auxiliary Output Current Limit
Current which must be drawn from
0.84
A
time-out
0.375
0.7
1.35
A
= 6.0V
1600
Ω
= 1.65V
150
Ω
= 1.65V
430
Ω
µs
µs
µs
Delay from 12V[A/B] Overcurrent
MIC2592B-2BTQ
1
µs
Delay from 3V[A/B] Overcurrent
MIC2592B-2BTQ
1
µs
Delay from VAUX[A/B] Overcurrent
MIC2592B-2BTQ
1
µs
250
µs
Symbol
Parameter
Condition
Min
Typ
Max Units
Auxiliary Output Current Limit
Current which must be drawn from
0.84
A
Symbol
Parameter
Condition
Min
Typ
Max Units
Auxiliary Output Current Limit
Current which must be drawn from
0.84
A
SCL (clock) period
Figure 1
Data In setup time to SCL HIGH
Figure 1
Data Out stable after SCL LOW
Figure 1
Data LOW setup time to SCL LOW
Start condition, Figure 1
Data HIGH hold time after SCL HIGH Stop condition, Figure 1
SCL (clock) period
Figure 1
Data In setup time to SCL HIGH
Figure 1
Data Out stable after SCL LOW
Figure 1
Data LOW setup time to SCL LOW
Start condition, Figure 1
Data HIGH hold time after SCL HIGH Stop condition, Figure 1
µs
ns
ns
ns
ns
µs
ns
ns
ns
ns
µs
ns
ns
ns
ns


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