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ADSP-2196MKST-160X Datasheet(PDF) 2 Page - Analog Devices |
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ADSP-2196MKST-160X Datasheet(HTML) 2 Page - Analog Devices |
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2 / 68 page  For current information contact Analog Devices at 800/262-5643 ADSP-2196 September 2001 This information applies to a product under development. Its characteristics and specifications are subject to change with- out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. 2 REV. PrA 35(/,0,1$5< 7(&+1,&$/ '$7$ ADSP-2196 DSP FEATURES 16K Words of On-Chip RAM, Configured as 8K Words On-Chip 24-bit RAM and 8K Words On-Chip 16-bit RAM 16K Words of On-Chip 24-bit ROM Architecture Enhancements beyond ADSP-218x Family are Supported with Instruction Set Extensions for Added Registers, Ports, and Peripherals Flexible Power Management with Selectable Power-Down and Idle Modes Programmable PLL Supports 1 to 32 Frequency Multiplication, Enabling Full-Speed Operation from Low-Speed Input Clocks 2.5 V Internal Operation Supports 3.3 V Compliant I/O Three Full-Duplex Multichannel Serial Ports, Each Supporting H.100 Standard with A-Law and -Law Companding in Hardware Two SPI-Compatible Ports with DMA Capability One UART Port with DMA Capability 16 General-Purpose I/O Pins (Eight Dedicated/Eight Programmable from the External Memory Interface) with Integrated Interrupt Support Three Programmable 32-Bit Interval Timers with Pulsewidth Counter, PWM Generation, and Externally Clocked Timer Capabilities Up to 11 DMA Channels can be Active at any Given Time Host Port With DMA Capability for Efficient, Glueless Host Interface (16-Bit Transfers) External Memory Interface Features Include: Direct Access from the DSP to External Memory for Data and Instructions. Support for DMA Block Transfers to/from External Memory. Separate Peripheral Memory Space with Parallel Support for 224K External 16-Bit Registers. Four General-Purpose Memory Select Signals that Provide Access to Separate Banks of External Memory. Bank Boundaries and Size Are User- Programmable. Programmable Waitstate Logic with ACK Signal and Separate Read and Write Wait Counts. Wait Mode Completion Supports All Combinations of ACK and/or Wait Count. I/O Clock Rate Can Be Set to the Peripheral Clock Rate Divided by 1, 2, 4, 16, or 32 to Allow Interface to Slow Memory Devices. Address Translation and Data Word Packing is Provided to Support an 8- or 16-Bit External Data Bus. Programmable Read and Write Strobe Polarity. Separate Configuration Registers for the Four General-Purpose, Peripheral, and Boot Memory Spaces. Bus Request and Grant Signals Support the Use of the External Bus by an External Device. Boot Methods Include Booting Through External Memory Interface, SPI Ports, UART Port, or Host Interface IEEE JTAG Standard 1149.1 Test Access Port Supports On-Chip Emulation and System Debugging 144-Lead LQFP Package (20 20 1.4 mm) and 144-Lead Mini-BGA Package (10 10 1.25 mm) |
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