7

AT24C02A/04A/08A/16A

5083A–SEEPR–9/04

MEMORY RESET: After an interruption in protocol, power loss or system reset, any

two-wire part can be reset by following these steps:

1.

Clock up to 9 cycles.

2.

Look for SDA high in each cycle while SCL is high.

3.

Create a start condition as SDA is high.

Figure 4. Bus Timing

Figure 5. Write Cycle Timing

Note:

The write cycle time t

t

wr

(1)

STOP

CONDITION

START

CONDITION

WORDn

ACK

8th BIT

SCL

SDA