CY2277A
Document #: 38-07332 Rev. *A
Page 11 of 19
Switching Characteristics (-12)[9, 10, 11]
Parameter
Output
Description
Test Conditions
Min.
Typ.
Max.
Unit
t1
All Clocks
Output Duty Cycle[12]
t1 = t1A ÷ t1B
45
50
55
%
t2
CPUCLK,
IOAPIC
CPU and IOAPIC Clock
Rising and Falling Edge
Rate
Between 0.6V and 1.8V, VDDCPU = 2.5V
Between 0.4V and 2.4V, VDDCPU = 3.3V
CPU clocks at 66.6 MHz
1.0
1.0
4.0
4.0
V/ns
t2
PCI
PCI Clock Rising and
Falling Edge Rate
Between 0.4V and 2.4V, VDDCPU = 3.3V
1.0
4.0
V/ns
t2
REF0
REF0 Clock Rising and
Falling Edge Rate
Between 0.8V and 2.4V, VDDCPU = 3.3V
1.0
4.0
V/ns
t2
SDRAM
SDRAM Rising and Fall-
ing Edge Rate
Between 0.5V and 2.0V
SDRAM clocks at 66.6 MHz
1.5
4.0
V/ns
t2
REF1
USBCLK
IOCLK
REF1, USB and IO Rising
and Falling Edge Rate
Between 0.4V and 2.4V
0.5
2.0
V/ns
t3
CPUCLK
CPU Clock Rise Time
Between 0.4V and 2.0V, VDDCPU = 2.5V
Between 0.4V and 2.4V, VDDCPU = 3.3V
0.4
0.4
2.0
2.0
ns
t3
USBCLK,
IOCLK
USB Clock and I/O Clock
Rise Time
Between 0.4V and 2.4V
1.0
4.0
ns
t4
CPUCLK
CPU Clock Fall Time
Between 2.0V and 0.4V, VDDCPU = 2.5V
Between 2.4V and 0.4V, VDDCPU = 3.3V
0.4
0.4
2.0
2.0
ns
t4
USBCLK,
IOCLK
USB Clock and I/O Clock
Fall Time
Between 2.4V and 0.4V
1.0
4.0
ns
t5
CPUCLK
CPU-CPU Clock Skew
Measured at 1.25V, VDDCPU = 2.5V
100
250
ps
t6
CPUCLK,
PCICLK
CPU-PCI Clock Skew
(-12)
Measured at 1.25V for 2.5V clocks, and
at 1.5V for 3.3V clocks
1.0
4.0
ns
t7
CPUCLK,
SDRAM
CPU-SDRAM Clock
Skew
Measured at 1.25V for 2.5V clocks, and
at 1.5V for 3.3V clocks, VDDCPU = 2.5V
500
ps
t8
CPUCLK
Cycle-Cycle Clock Jitter
Measured at 1.25V for 2.5V clocks and
at 1.5V for 3.3V clocks
250
ps
t8
PCICLK
Cycle-Cycle Clock Jitter
Measured at 1.5V
500
ps
t9
CPUCLK,
PCICLK,
SDRAM
Power-up Time
CPU, PCI, and SDRAM clock stabiliza-
tion from power-up
3
ms
t10
CPU, PCI,
SDRAM
Frequency Slew Rate
Rate of change of frequency
2
MHz/
ms