CY25200
Document #: 38-07633 Rev. *A
Page 2 of 11
General Description
The CY25200 is a Spread Spectrum Clock Generator (SSCG)
IC used for the purpose of reducing Electro Magnetic Inter-
ference (EMI) found in today’s high-speed digital electronic
systems.
The device uses a Cypress proprietary Phase-Locked Loop
(PLL) and Spread Spectrum Clock (SSC) technology to
synthesize and modulate the frequency of the input clock. By
frequency modulating the clock, the measured EMI at the
fundamental and harmonic frequencies are greatly reduced.
This reduction in radiated energy can significantly reduce the
cost of complying with regulatory agency requirements (EMC)
and improve time to market without degrading system perfor-
mance.
The CY25200 uses a factory-programmable configuration
memory array to synthesize output frequency, spread %,
crystal load capacitor, clock control pins, PD# and OE options.
The spread % is factory programmed to either center spread
or down spread with various spread percentages. The range
for center spread is from ±0.25% to ±2.50%. The range for
down spread is from –0.5% to –5.0%. Contact the factory for
smaller or larger spread % amounts if required.
The input to the CY25200 can be either a crystal or a clock
signal. The input frequency range for crystals is 8–30 MHz,
and for clock signals is 8–166 MHz.
The CY25200 has six clock outputs, SSCLK1 to SSCLK6. The
frequency modulated SSCLK outputs can be programmed
from 3–200 MHz.
The CY25200 products are available in a 16-pin TSSOP
package with a commercial operating temperature range of 0
to 70
°C.
CY25200 Pin Summary
Name
Pin Number
Description
XIN
1
Crystal Input or Reference Clock Input.
XOUT
16
Crystal Output. Leave this pin floating if external clock is used.
VDD
2
3.3V Power supply for digital logic and SSCLK5/6 clock drives.
AVDD
3
3.3V analog–PLL power supply
VSS
13
Ground
AVSS
5
Analog ground
VDDL
11
2.5V or 3.3V power supply for SSCLK1/2/3/4 clock drives
VSSL
6
VDDL power supply ground
SSCLK1
7
Programmable Spread Spectrum Clock Output at VDDL Level (2.5V or 3.3V)
SSCLK2
8
Programmable Spread Spectrum Clock Output at VDDL Level (2.5V or 3.3V)
SSCLK3
9
Programmable Spread Spectrum Clock Output at VDDL Level (2.5V or 3.3V)
SSCLK4
12
Programmable Spread Spectrum Clock Output at VDDL Level (2.5V or 3.3V)
SSCLK5/REFOUT/CP2
14
Programmable Spread Spectrum Clock or Buffered Reference Output at VDD
Level (3.3V) or Control pin, CP2
SSCLK6/REFOUT/CP3
15
Programmable Spread Spectrum Clock or Buffered Reference Output at VDD
Level (3.3V) or Control pin, CP3
CP0[1]
4
Control Pin 0
CP1[1]
10
Control Pin 1
Note:
1. Pins can be programmed to be any of the following control signals: OE: Output Enable, OE = 1 all the SSCLK outputs are enabled, PD#: Powerdown, PD#
= 0, all the SSCLK outputs are three-stated and the part enters a low-power state, SSON: Spread Spectrum Control (SSON = 0, No Spread and SSON = 1,
Spread Signal), CLKSEL: SSCLK Output Frequency Select. Please see page 3 for control pins programming option.
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