CY28347
Document #: 38-07352 Rev. *C
Page 9 of 22
Maximum Ratings[3]
Input Voltage Relative to VSS:.............................. VSS – 0.3V
Input Voltage Relative to VDDQ or AVDD: ............. VDD + 0.3V
Storage Temperature: ................................–65
°C to + 150°C
Operating Temperature: .................................... 0
°C to +70°C
Maximum ESD .............................................................2000V
Maximum Power Supply: ................................................5.5V
This device contains circuitry to protect the inputs against
damage due to HIGH static voltages or electric field. However,
precautions should be take to avoid application of any voltage
higher than the maximum rated voltages to this circuit. For
proper operation, VIN and VOUT should be constrained to the
range.
VSS < (VIN or VOUT) < VDD
Unused inputs must always be tied to an appropriate logic
voltage level (either VSS or VDD).
DC Parameters (VDD = VDDPCI = VDDAGP = VDDR = VDD48M = VDDC = 3.3V ± 5%, VDDI = VDD = 2.5 ± 5%, TA = 0 °C to +70 °C)
Parameter
Description
Conditions
Min.
Typ.
Max.
Unit
VIL1
Input LOW Voltage
Applicable to PD#, F S(0:4)
1.0
Vdc
VIH1
Input HIGH Voltage
2.0
Vdc
VIL2
Input LOW Voltage
Applicable to SDATA and SCLK
1.0
Vdc
VIH2
Input HIGH Voltage
2.2
Vdc
Vol
Output LOW Voltage for Sreset#
IOL
0.4
V
Iol
Pull-down Current for Sreset#
VOL = 0.4V
24
35
mA
Ioz
Three-state Leakage Current
10
µA
Idd3.3V
Dynamic Supply Current
CPU frequency set at 133.3[4]
156
180
mA
Idd2.5V
Dynamic Supply Current
CPU frequency set at 133.3 MHz[4]
177
200
mA
Ipd
Power-down Supply current
PD# = 0
3.8
4.0
mA
Ipup
Internal Pull-up Device Current
Input @ VSS
–25
µA
Ipdwn
Internal Pull-down Device Current
Input @ VDD
10
µA
Cin
Input Pin Capacitance
5pF
Cout
Output Pin Capacitance
6pF
Lpin
Pin Inductance
7pF
Cxtal
Crystal Pin Capacitance
Measured from the XIN or XOUT to VSS
27
36
45
pF
AC Parameters
Parameter
Description
66 MHz
100 MHz
133 MHz
200 MHz
Unit
Notes
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Crystal
TDC
Xin Duty Cycle
45554555
45
55
45
55
% 5,6,7,8
TPeriod
Xin Period
69.84
71.0
69.84
71.0
69.84
71.0
69.84
71.0
ns 5,6,7,8
VHIGH
Xin HIGH Voltage
0.7VDD
VDD
0.7VDD
VDD
0.7VDD
VDD
0.7VDD
VDD
V7,9
VLOW
Xin LOW Voltage
0
0.3VDD
00.3VDD
00.3VDD
00.3VDD V
Tr / Tf
Xin Rise and Fall Times
10.0
10.0
10
10
ns 7
TCCJ
Xin Cycle to Cycle Jitter
500
500
500
500
ps 10,11,12,13
Txs
Crystal Start-up Time
30
30
30
30
ms 9
Notes:
3.
Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
4.
All outputs loaded as per maximum capacitative load table in P4 and DDR mode. See Table 11.
5.
All outputs loaded as per loading specified in the loading table. See Table 11.
6.
This measurement is applicable with Spread ON or spread OFF.
7.
This is required for the duty cycle on the REF clock out to be as specified. The device will operate reliably with input duty cycles up to 30/70 but the REF clock
duty cycle will not be within data sheet specifications.
8.
The typical value of VX is expected to be 0.5*VDDD (or 0.5*VDDC for CPUCS signals) and will track the variations in the DC level of the same.
9.
Measured between 0.2Vdd and 0.7Vdd.
10. Probes are placed on the pins, and measurements are acquired between 0.4V and 2.4V for 3.3V signals and between 0.4V and 2.0V for 2.5V signals, and
between 20% and 80% for differential signals.
11.
Probes are placed on the pins, and measurements are acquired at 2.4V for 3.3V signals and at 2.0V for 2.5V signals.
12. When Xin is driven from and external clock source (3.3V parameters apply).
13. When Crystal meets minimum 40 ohm device series resistance specification.
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
