CY7C1355B
CY7C1357B
Document #: 38-05117 Rev. *B
Page 9 of 33
TMS
-
U2
R5
JTAG serial
input
Synchronous
Serial data-In to the JTAG circuit. Sampled on the rising
edge of TCK. If the JTAG feature is not being utilized, this
pin can be disconnected or connected to VDD. This pin is
not available on TQFP packages.
TCK
-
U4
R7
JTAG-Clock
Clock input to the JTAG circuitry. If the JTAG feature is
not being utilized, this pin must be connected to VSS. This
pin is not available on TQFP packages.
NC
16,38,39,42,
43,66,84
B1,C1,R1,
T1,T2,J3,
A4,D4,L4,
J5,R5,T6,
U6,B7,C7,
R7
A1,A11,B1,
B9,B11,C2,
C10,H1,H3,
H9,H10,N2,
N5,N6,N7,
N10,P1,P2,
P11,R2
-
No Connects. Not internally connected to the die.
18M,36M, 72M, 144M and 288M are address expansion
pins and are not internally connected to the die.
VSS/DNU
14
-
-
Ground/DNU
This pin can be connected to Ground or should be left
floating.
CY7C1357B–Pin Definitions
Name
TQFP
BGA
fBGA
I/O
Description
A0, A1, A
37,36,32,33,
34,35,44,45,
46,47,48,49,
50,80,81,82,
83,99,100
P4,N4,A2,
C2,R2,T2,
A3,B3,C3,
T3,A5,B5,
C5,T5,A6,
C6,R6,T6
R6,P6,A2,
A9,A10,A11,
B2,B10,P3,
P4,P8,P9,
P10,R3,R4,
R8,R9,R10,
R11
Input-
Synchronous
Address Inputs used to select one of the 512K address
locations. Sampled at the rising edge of the CLK. A[1:0]
are fed to the two-bit burst counter.
BWA,BWB
93,94
G3,L5
B5,A4
Input-
Synchronous
Byte Write Select Inputs, active LOW. Qualified with WE
to conduct Writes to the SRAM. Sampled on the rising
edge of CLK.
WE
88
H4
B7
Input-
Synchronous
Write Enable Input, active LOW. Sampled on the rising
edge of CLK if CEN is active LOW. This signal must be
asserted LOW to initiate a Write sequence.
ADV/LD
85
B4
A8
Input-
Synchronous
Advance/Load Input. Used to advance the on-chip ad-
dress counter or load a new address. When HIGH (and
CEN is asserted LOW) the internal burst counter is ad-
vanced. When LOW, a new address can be loaded into
the device for an access. After being deselected, ADV/LD
should be driven LOW in order to load a new address.
CLK
89
K4
B6
Input-
Clock
Clock Input. Used to capture all synchronous inputs to
the device. CLK is qualified with CEN. CLK is only recog-
nized if CEN is active LOW.
CE1
98
E4
A3
Input-
Synchronous
Chip Enable 1 Input, active LOW. Sampled on the rising
edge of CLK. Used in conjunction with CE2, and CE3 to
select/deselect the device.
CE2
97
B2
B3
Input-
Synchronous
Chip Enable 2 Input, active HIGH. Sampled on the rising
edge of CLK. Used in conjunction with CE1 and CE3 to
select/deselect the device.
CE3
92
B6
A6
Input-
Synchronous
Chip Enable 3 Input, active LOW. Sampled on the rising
edge of CLK. Used in conjunction with CE1 and CE2 to
select/deselect the device.
CY7C1355B–Pin Definitions (continued)
Name
TQFP
BGA
fBGA
I/O
Description
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