CY7C006A/CY7C007A
CY7C016A/CY7C017A
Document #: 38-06045 Rev. *C
Page 9 of 20
Data Retention Mode
The CY7C006A, CY7C007A, CY7C016A, and CY7C017A are
designed with battery backup in mind. Data retention voltage
and supply current are guaranteed over temperature. The
following rules ensure data retention:
1. Chip Enable (CE) must be held HIGH during data retention,
within VCC to VCC – 0.2V.
2. CE must be kept between VCC – 0.2V and 70% of VCC
during the power-up and power-down transitions.
3. The RAM can begin operation >tRC after VCC reaches the
minimum operating voltage (4.5 volts).
tWB
R/W HIGH after BUSY (Slave)
0
0
0
ns
tWH
R/W HIGH after BUSY HIGH (Slave)
11
13
15
ns
tBDD[20]
BUSY HIGH to Data Valid
12
15
20
ns
INTERRUPT TIMING[18]
tINS
INT Set Time
12
15
20
ns
tINR
INT Reset Time
12
15
20
ns
SEMAPHORE TIMING
tSOP
SEM Flag Update Pulse (OE or SEM)10
10
10
ns
tSWRD
SEM Flag Write to Read Time
5
5
5
ns
tSPS
SEM Flag Contention Window
5
5
5
ns
tSAA
SEM Address Access Time
12
15
20
ns
Switching Characteristics Over the Operating Range[12] (continued)
Parameter
Description
CY7C006A
CY7C007A
CY7C016A
CY7C017A
Unit
–12[1]
–15
–20
Min.
Max.
Min.
Max.
Min.
Max.
Timing
Parameter
Test Conditions[21]
Max.
Unit
ICCDR1
@ VCCDR = 2V
1.5
mA
Data Retention Mode
4.5V
4.5V
VCC > 2.0V
VCC to VCC – 0.2V
VCC
CE
tRC
V
IH
Switching Waveforms
Read Cycle No. 1 (Either Port Address Access)[22, 23, 24]
Notes:
20. tBDD is a calculated parameter and is the greater of tWDD–tPWE (actual) or tDDD–tSD (actual).
21. CE = VCC, Vin = GND to VCC, TA = 25°C. This parameter is guaranteed but not tested.
22. R/W is HIGH for read cycles.
23. Device is continuously selected CE = VIL. This waveform cannot be used for semaphore reads.
24. OE = VIL.
tRC
tAA
tOHA
DATA VALID
PREVIOUS DATA VALID
DATA OUT
ADDRESS
tOHA