CY7C1355B-117BZC datasheet(11/33 Pages) CYPRESS

Part #	CY7C1355B-117BZC

Description	9-Mb (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture

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Manufacturer	CYPRESS [Cypress Semiconductor]

Direct Link	http://www.cypress.com

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11 / 33 page

CY7C1355B

CY7C1357B

Document #: 38-05117 Rev. *B

Page 11 of 33

VSS

5,10,17,21,

26,40,55,60,

67,71,76,90

D3,D5,E3,

E5,F3,F5,

G5,H3,

H5,K3,K5,

L3,M3,

M5,N3,

N5,P3,P5

C4,C5,C6,

C7,C8,D5,

D6,D7,E5,

E6,E7,F5,

F6,F7,G5,

G6,G7,H5,

H6,H7,J5,

J6,J7,K5,K6,

K7,L5,L6,L7,

M5,M6,M7,

N4,N8

Ground

Ground for the device.

TDO

-

U5

P7

JTAG serial

output

Synchronous

Serial data-out to the JTAG circuit. Delivers data on the

negative edge of TCK. If the JTAG feature is not being

utilized, this pin should be left unconnected. This pin is not

available on TQFP packages.

TDI

-

U3

P5

JTAG serial

input

Synchronous

Serial data-In to the JTAG circuit. Sampled on the rising

edge of TCK. If the JTAG feature is not being utilized, this

pin can be left floating or connected to VDD through a pull

up resistor. This pin is not available on TQFP packages.

TMS

-

U2

R5

JTAG serial

input

Synchronous

Serial data-In to the JTAG circuit. Sampled on the rising

edge of TCK. If the JTAG feature is not being utilized, this

pin can be disconnected or connected to VDD. This pin is

not available on TQFP packages.

TCK

-

U4

R7

JTAG-Clock

Clock input to the JTAG circuitry. If the JTAG feature is

not being utilized, this pin must be connected to VSS. This

pin is not available on TQFP packages.

NC

1,2,3,6,7,16,

25,28,29,30,

38,39,42,43,

51,52,53,56,

57,66,75,78,

79,84,95,96

A4,B1,B7,

C1,C7,D2,

D4,D7,E1,

E6,H2,F2,

G1,G6,

H7,J3,J5,

K1,K6,L4,

L2,L7,M6,

N2,N7,L7,

P1,P6,R1,

R5,R7,T1,

T4,U6

A1,A5,B1,

B4,B9,B11,

C1,C2,C10,

D1,D10,E1,

E10,F1,F10,

G1,G10,H1,

H3,H9,H10,

J2,J11,K2,

K11,L2,L11,

M2,M11,N2,

N5,N6,N7,

N10,N11,P1,

P2,P11,R2

-

No Connects. Not internally connected to the die.

18M,36M, 72M, 144M and 288M are address expansion

pins and are not internally connected to the die.

VSS/DNU

14

-

Ground/DNU

This pin can be connected to Ground or should be left

floating.

CY7C1357B–Pin Definitions (continued)

Name

TQFP

BGA

fBGA

I/O

Description

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