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DS1854B-050 Datasheet(PDF) 11 Page - Maxim Integrated Products |
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DS1854B-050 Datasheet(HTML) 11 Page - Maxim Integrated Products |
11 / 22 page Dual Temperature-Controlled Resistors with Two Monitors ____________________________________________________________________ 11 Variable Resistors The value of each variable resistor is determined by a temperature-addressed look-up table, which can assign a unique value (00h to FFh) to each resistor for every 2°C increment over the -40°C to +102°C range (see Table 3). See the Temperature Conversion section for more information. A resistor disable feature places both outputs in a high- impedance mode. This occurs when the RHIZ input is high. An internal pullup of RRHIZ is provided, readying this pin for input from the Tx Disable signal as specified in the SFF and SFP MSA. The variable resistors can also be used in manual mode. If the TEN bit equals 0, then the resistors are in manual mode and the temperature indexing is dis- abled. The user sets the resistors in manual mode by writing to addresses 82h and 83h in Table 01 to control resistors 0 and 1, respectively. Memory Description Main and auxiliary memories can be accessed by two separate device addresses. The Main Device address is A2h (or value in Table 01, byte 8Ch when ADFIX = 1) and the Auxiliary Device address is A0h. A user option is provided to respond to one or two device addresses. This feature can be used to save component count in SFF applications (Main Device address can be used) or other applications where both GBIC (Auxiliary Device address can be used) and monitoring functions are implemented and two device addresses are need- ed. The memory blocks are enabled with the corre- sponding device address. Memory space from 80h and up is accessible only through the Main Device address. This memory is organized as three tables; the desired table can be selected by the contents of memory loca- tion 7Fh, Main Device. The Auxiliary Device address has no access to the tables, but the Auxiliary Device address can be mapped into the Main Device’s memo- ry space as a fourth table. Device addresses are pro- grammable with two control bits in EEPROM. ADEN configures memory access to respond to differ- ent device addresses (see Tables 4 and 5). The default device address for EEPROM-generated addresses is A2h. If the ADEN bit is 1, additional 128 bytes of EEPROM are accessible through the Main Device, selected as Table 00 (see Figure 3). In this configuration, the Auxiliary Device address is not accessible. APEN con- trols the protection of Table 00 regardless of the setting of ADEN. ADFIX (address fixed) determines whether the Main Device address is determined by an EEPROM byte (Table 01, byte 8Ch, when ADFIX =1). There can be up to 128 devices sharing a common 2-wire bus, with each device having its own unique device address. Memory Protection Memory access from either device address can be either read/write or read only. Write protection is accom- plished by a combination of control bits in EEPROM (APEN and MPEN in configuration register 89h) and a write-protect enable (WPEN) pin. Since the WPEN pin is often not accessible from outside the module, this scheme effectively allows the module to be locked by the manufacturer to prevent accidental writes by the end user. Separate write protection is provided for the Auxiliary and Main Device address through distinct bits APEN and MPEN. APEN and MPEN are bits from configura- tion register 89h, Table 01. Due to the location, the APEN and MPEN bits can only be written through the Main Device address. The control of write privileges through the Auxiliary Device address is dependent on the value of APEN. Care should be taken with the set- ting of MPEN, once set to a 1, assuming WPEN is high, access through the Main Device is thereafter denied unless WPEN is taken to a low level. By this means inadvertent end-user write access can be denied. Main Device address space 60h to 7Fh is SRAM and is not write protected by APEN, MPEN, or WPEN. For example, the user may reset flags set by the device. Bytes designated as “Reserved” may be used as scratchpad, but they will not be stored in a power cycle because of their volatility. These bytes are reserved for added functionality in future versions of this device. Note that in single device mode (ADEN bit = 1), APEN deter- mines the protection level of Table 00, independent of WPEN. The write-protect operation, for both Main and Auxiliary Devices, is summarized in the Tables 6 and 7. WPEN MPEN PROTECT MAIN 0X No X0 No 11 Yes Table 6. Main Device APEN WPEN PROTECT AUXILIARY 0 XNo 1 X Yes Table 7. Auxiliary Device |
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