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FMS6408MTC144 Datasheet(PDF) 5 Page - Fairchild Semiconductor |
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FMS6408MTC144 Datasheet(HTML) 5 Page - Fairchild Semiconductor |
5 / 9 page REV. 2C August 31, 2004 5 FMS6408 DATA SHEET Pin Configuration Pin# Pin Type Description 1YINA Input Y (Luminance) or Green input A, must be connected to a signal which includes sync 2UINA Input U or Blue input A 3VINA Input V or Red input A 4 GND Input Must be tied to ground, do not float 5YINB Input Y (Luminance) or Green input B, must be connected to a signal which includes sync 6UINB Input U or Blue input B 7VINB Input V or Red input B 8INMUX (A/B) Input Mux select, A = ‘1’, B = ‘0’, must be externally tied high or low 9VOUT Output V or Red output 10 GND Input Must to be tied to ground, do not float 11 UOUT Output U or Blue output 12 BYPASS (Bypass/Filter) Input Filter bypass, BYPASS = ‘1’, FILTER = ‘0’, must be externally tied high or low 13 YOUT Output Y or Green output 14 VCC Input +5V supply Functional Description Introduction This product is a three channel monolithic continuous time video filter designed for reconstructing YUV, YC CV or RGB signals from a video D/A source. Inputs should be AC coupled while outputs can be either AC or DC coupled. The reconstruction filters approximate a 5th order Butter- worth response optimized for minimum overshoot and flat group delay. This provides a maximally flat response in terms of delay and amplitude. Each of the three outputs is capable of driving 2Vpp into 75 Ω loads. All channels are clamped during the sync interval to set the appropriate dc output level. Sync tip clamping greatly reduces the effective input time constant allowing the use of small low cost input coupling capacitors. The input will settle to 10mV in 2ms for typical DC shifts present in the video signal. In most applications the input coupling capacitors are 0.1 µF. The inputs typically sink 1uA of current during active video. For YUV signals, this translates into a 2mV tilt in a horizon- tal line at the Y output. During sync, the clamp restores this leakage current by sourcing an average of 20 µA over the clamp interval. Any change in the coupling capacitor values will affect the amount of tilt per line. Any reduction in tilt will come with an increase in settling time. Sync processing is based on the Y/G input channel in all operating modes. Inputs The inputs will typically be driven by either a low impedance source of 1Vpp or the output of a 75 Ω terminated line driven by the output of a current DAC. In either case, the inputs must be capacitively coupled to allow the sync-detect and DC restore circuitry to operate properly. Outputs The outputs are low impedance voltage drivers which can handle either a single or dual load. A single load consists of a 75 Ω series termination resistor feeding a 75Ω terminated line for a total load at the part of 150 Ω. Even when two loads are present (75 Ω) the driver will produce a full 2Vpp signal at its output pin. The driver can also be used to drive an AC coupled single or dual load. When driving a dual load either output will still function if the other output connection is inadvertently shorted providing these loads are AC coupled. FMS6408 14-pin TSSOP YINA VCC UINA VINA BYPASS GND Y INB GND INMUX (A/B) UINB VINB YOUT UOUT VOUT 1 2 3 4 5 6 7 14 13 12 11 10 9 8 |
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