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HFA3863 Datasheet(PDF) 8 Page - Intersil Corporation |
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HFA3863 Datasheet(HTML) 8 Page - Intersil Corporation |
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8 / 39 page  4-8 Power Down Modes The power consumption modes of the HFA3863 are controlled by the following control signals. Receiver Power Enable (RX_PE, pin 61), which disables the receiver when inactive. Transmitter Power Enable (TX_PE, pin 62), which disables the transmitter when inactive. Reset (RESET, pin 63), which puts the receiver in a sleep mode. The power down mode where, both RESET and RX_PE are used is the lowest possible power consumption mode for the receiver. Exiting this mode requires a maximum of 10 µs before the device is operational. The contents of the Configuration Registers are not effected by any of the power down modes. No reconfiguration is required when returning to operational modes. Activation of RESET does NOT corrupt learned values of AGC settings and noise floor values. Table 2 describes the power down modes available for the HFA3863 (VCC = 3.3V). The table values assume that all other inputs to the part (MCLK, SCLK, etc.) continue to run except as noted. Transmitter Description The HFA3863 transmitter is designed as a Direct Sequence Spread Spectrum Phase Shift Keying (DSSS PSK) modulator. It can handle data rates of up to 11Mbps (refer to AC and DC specifications). The various modes of the modulator are Differential Binary Phase Shift Keying (DBPSK) for 1Mbps, Differential Quaternary Phase Shift Keying (DQPSK) for 2Mbps, and Complementary Code Keying (CCK) for 5.5Mbps and 11Mbps. These implement data rates as shown in Table 3. The major functional blocks of the transmitter include a network processor interface, DPSK modulator, high rate modulator, a data scrambler and a spreader, as shown in Figure 7. CCK is essentially a quadra-phase form of M-ARY Orthogonal Keying. A description of that modulation can be found in Chapter 5 of: “Telecommunications System Engineering”, by Lindsey and Simon, Prentis Hall publishing. The preamble is always transmitted as the DBPSK waveform while the header can be configured to be either DBPSK, or DQPSK, and data packets can be configured for DBPSK, DQPSK, or CCK. The preamble is used by the receiver to achieve initial PN synchronization while the header includes the necessary data fields of the communications protocol to establish the physical layer link. The transmitter generates the synchronization preamble and header and knows when to make the DBPSK to DQPSK or CCK switchover, as required. RX_RF_AGC RX_IF_DET THRESH. IF DAC I ADC Q ADC RX_Q ± RX_I ± RX_IF_AGC HFA3683 HFA3783 HFA3863 6 6 7 1 1 I/O DEMOD AGC DATA I/O DETECT CTL FIGURE 6. AGC CIRCUIT TABLE 2. POWER DOWN MODES MODE RX_PE TX_PE RESET AT 44MHz DEVICE STATE SLEEP Inactive Inactive Active 1mA Both transmit and receive functions disabled. Device in sleep mode. Control Interface is still active. Register values are maintained. Device will return to its active state within 10 µs. STANDBY Inactive Inactive Inactive 1.5mA Both transmit and receive operations disabled. Device will resume its operational state within 1 µs of RX_PE or TX_PE going active. TX Inactive Active Inactive 15mA Receiver operations disabled. Receiver will return in its operational state within 1 µs of RX_PE going active. RX Active Inactive Inactive 50mA Transmitter operations disabled. Transmitter will return to its operational state within 2 MCLKs of TX_PE going active. NO CLOCK ICC Standby Active 300 µA All inputs at VCC or GND. HFA3863 |
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