IC41C16256

IC41LV16256

10

Integrated Circuit Solution Inc.

DR018-0C 04/23/2004

Notes:

1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycle (RAS-Only or CBR) before proper device

in a monotonic manner.

6. Measured with a load equivalent to one TTL gate and 50 pF.

9. If CAS is LOW at the falling edge of RAS, data out will be maintained from the previous cycle. To initiate a new cycle and clear the

the selected cell. If neither of the above conditions is met, the state of I/O (at access time and until CAS and RAS or OE go back

15. Output parameter (I/O) is referenced to corresponding CAS input, I/O0-I/O7 by LCAS and I/O8-I/O15 by UCAS.

16. During a READ cycle, if OE is LOW then taken HIGH before CAS goes HIGH, I/O goes open. If OE is tied permanently LOW, a LATE

WRITE or READ-MODIFY-WRITE is not possible.

17. Write command is defined as WE going low.

that the output buffers will be open during the WRITE cycle. The I/Os will provide the previously written data if CAS remains LOW

20. The first

χCAS edge to transition LOW.

21. The last

χCAS edge to transition HIGH.

22. These parameters are referenced to CAS leading edge in EARLY WRITE cycles and WE leading edge in LATE WRITE or READ-

MODIFY-WRITE cycles.

23. Last falling

χCAS edge to first rising χCAS edge.

24. Last rising

χCAS edge to next cycle’s last rising χCAS edge.

25. Last rising

χCAS edge to first falling χCAS edge.

26. Each

χCAS must meet minimum pulse width.

27. Last

χCAS to go LOW.

28. I/Os controlled, regardless UCAS and LCAS.

29. The 3 ns minimum is a parameter guaranteed by design.

30. Enables on-chip refresh and address counters.