Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.NET

X  

IDT72V261LA15TF Datasheet(PDF) 7 Page - Integrated Device Technology

Part # IDT72V261LA15TF
Description  3.3 VOLT CMOS SuperSync FIFO
Download  27 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

IDT72V261LA15TF Datasheet(HTML) 7 Page - Integrated Device Technology

Back Button IDT72V261LA15TF Datasheet HTML 3Page - Integrated Device Technology IDT72V261LA15TF Datasheet HTML 4Page - Integrated Device Technology IDT72V261LA15TF Datasheet HTML 5Page - Integrated Device Technology IDT72V261LA15TF Datasheet HTML 6Page - Integrated Device Technology IDT72V261LA15TF Datasheet HTML 7Page - Integrated Device Technology IDT72V261LA15TF Datasheet HTML 8Page - Integrated Device Technology IDT72V261LA15TF Datasheet HTML 9Page - Integrated Device Technology IDT72V261LA15TF Datasheet HTML 10Page - Integrated Device Technology IDT72V261LA15TF Datasheet HTML 11Page - Integrated Device Technology Next Button
Zoom Inzoom in Zoom Outzoom out
 7 / 27 page
background image
IDT72V261LA/72V271LA
3.3 VOLT CMOS SuperSync FIFO™ 16,384 x 9 and 32,768 x 9
7
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
If the FIFO is full, the first read operation will cause
FF to go HIGH.
Subsequent read operations will cause
PAF and HF to go HIGH at the
conditions described in Table 1. If further read operations occur, without
write operations,
PAE will go LOW when there are n words in the FIFO,
where n is the empty offset value. Continuing read operations will cause
the FIFO to become empty. When the last word has been read from the
FIFO, the
EF will go LOW inhibiting further read operations. REN is
ignored when the FIFO is empty.
When configured in IDT Standard mode, the
EF and FF outputs are
double register-buffered outputs.
Relevant timing diagrams for IDT Standard mode can be found in
Figure 7, 8 and 11.
FIRST WORD FALL THROUGH MODE (FWFT)
In this mode, the status flags,
IR, PAF, HF, PAE, and OR operate in
the manner outlined in Table 2. To write data into to the FIFO,
WEN
must be LOW. Data presented to the DATA IN lines will be clocked into
the FIFO on subsequent transitions of WCLK. After the first write is
performed, the Output Ready (
OR) flag will go LOW. Subsequent writes
will continue to fill up the FIFO.
PAE will go HIGH after n + 2 words
have been loaded into the FIFO, where n is the empty offset value. The
default setting for this value is stated in the footnote of Table 2. This
parameter is also user programmable. See section on Programmable
Flag Offset Loading.
If one continued to write data into the FIFO, and we assumed no
read operations were taking place, the
HF would toggle to LOW once
the 8,194th word for the IDT72V261LA and 16,386th word for the
IDT72V271LA, respectively was written into the FIFO. Continuing to
write data into the FIFO will cause the
PAF to go LOW. Again, if no
reads are performed, the
PAF will go LOW after (16,385-m) writes for
the IDT72V261LA and (32,769-m) writes for the IDT72V271LA, where
m is the full offset value. The default setting for this value is stated in
the footnote of Table 2.
When the FIFO is full, the Input Ready (
IR) flag will go HIGH, inhibit-
ing further write operations. If no reads are performed after a reset,
IR
will go HIGH after D writes to the FIFO. D = 16,385 writes for the
IDT72V261LA and 32,769 writes for the IDT72V271LA, respectively.
Note that the additional word in FWFT mode is due to the capacity of
the memory plus output register.
If the FIFO is full, the first read operation will cause the
IR flag to go
LOW. Subsequent read operations will cause the
PAF and HF to go
HIGH at the conditions described in Table 2. If further read operations
occur, without write operations, the
PAE will go LOW when there are n
+ 1 words in the FIFO, where n is the empty offset value. Continuing
read operations will cause the FIFO to become empty. When the last
word has been read from the FIFO,
OR will go HIGH inhibiting further
read operations.
REN is ignored when the FIFO is empty.
When configured in FWFT mode, the
OR flag output is triple register-
buffered, and the
IR flag output is double register-buffered.
Relevant timing diagrams for FWFT mode can be found in Figure 9,
10 and 12.
FUNCTIONAL DESCRIPTION
TIMING MODES:
IDT STANDARD VS FIRST WORD FALL THROUGH (FWFT) MODE
The IDT72V261LA/72V271LA support two different timing modes of
operation: IDT Standard mode or First Word Fall Through (FWFT) mode.
The selection of which mode will operate is determined during Master
Reset, by the state of the FWFT/SI input.
If, at the time of Master Reset, FWFT/SI is LOW, then IDT Standard
mode will be selected. This mode uses the Empty Flag (
EF) to indicate
whether or not there are any words present in the FIFO. It also uses the
Full Flag function (
FF) to indicate whether or not the FIFO has any free
space for writing. In IDT Standard mode, every word read from the
FIFO, including the first, must be requested using the Read Enable
(
REN) and RCLK.
If, at the time of Master Reset, FWFT/SI is HIGH, then FWFT mode
will be selected. This mode uses Output Ready (
OR) to indicate whether
or not there is valid data at the data outputs (Qn). It also uses Input
Ready (
IR) to indicate whether or not the FIFO has any free space for
writing. In the FWFT mode, the first word written to an empty FIFO
goes directly to Qn after three RCLK rising edges,
REN = LOW is not
necessary. Subsequent words must be accessed using the Read En-
able (
REN) and RCLK.
Various signals, both input and output signals operate differently
depending on which timing mode is in effect.
IDT STANDARD MODE
In this mode, the status flags,
FF, PAF, HF, PAE, and EF operate in
the manner outlined in Table 1. To write data into to the FIFO, Write
Enable (
WEN) must be LOW. Data presented to the DATA IN lines will
be clocked into the FIFO on subsequent transitions of the Write Clock
(WCLK). After the first write is performed, the Empty Flag (
EF) will go
HIGH. Subsequent writes will continue to fill up the FIFO. The Program-
mable Almost-Empty flag (
PAE) will go HIGH after n + 1 words have
been loaded into the FIFO, where n is the empty offset value. The
default setting for this value is stated in the footnote of Table 1. This
parameter is also user programmable. See section on Programmable
Flag Offset Loading.
If one continued to write data into the FIFO, and we assumed no
read operations were taking place, the Half-Full flag (
HF) would toggle
to LOW once the 8,193th word for IDT72V261LA and 16,385th word for
IDT72V271LA respectively was written into the FIFO. Continuing to
write data into the FIFO will cause the Programmable Almost-Full flag
(
PAF) to go LOW. Again, if no reads are performed, the PAF will go
LOW after (16,384-m) writes for the IDT72V261LA and (32,768-m) writes
for the IDT72V271LA. The offset “m” is the full offset value. The default
setting for this value is stated in the footnote of Table 1. This parameter
is also user programmable. See section on Programmable Flag Offset
Loading.
When the FIFO is full, the Full Flag (
FF) will go LOW, inhibiting
further write operations. If no reads are performed after a reset,
FF will
go LOW after D writes to the FIFO.
D = 16,384 writes for the
IDT72V261LA and 32,768 for the IDT72V271LA, respectively.


Similar Part No. - IDT72V261LA15TF

ManufacturerPart #DatasheetDescription
logo
Integrated Device Techn...
IDT72V261LA IDT-IDT72V261LA Datasheet
361Kb / 27P
   3.3 VOLT CMOS SuperSync FIFO
IDT72V261LA IDT-IDT72V261LA_14 Datasheet
361Kb / 27P
   3.3 VOLT CMOS SuperSync FIFO
More results

Similar Description - IDT72V261LA15TF

ManufacturerPart #DatasheetDescription
logo
Integrated Device Techn...
IDT72V285 IDT-IDT72V285 Datasheet
213Kb / 25P
   3.3 VOLT CMOS SuperSync FIFO
IDT72V275 IDT-IDT72V275_14 Datasheet
205Kb / 25P
   3.3 VOLT CMOS SuperSync FIFO
IDT72V261LA IDT-IDT72V261LA_14 Datasheet
361Kb / 27P
   3.3 VOLT CMOS SuperSync FIFO
IDT72V255LA IDT-IDT72V255LA_14 Datasheet
366Kb / 27P
   3.3 VOLT CMOS SuperSync FIFO
IDT72V281 IDT-IDT72V281_14 Datasheet
222Kb / 26P
   3.3 VOLT CMOS SuperSync FIFO
IDT72V2101 IDT-IDT72V2101 Datasheet
242Kb / 27P
   3.3 VOLT HIGH DENSITY CMOS SUPERSYNC FIFO
IDT72V2101 IDT-IDT72V2101_14 Datasheet
434Kb / 27P
   3.3 VOLT HIGH DENSITY CMOS SUPERSYNC FIFO
IDT72V291 IDT-IDT72V291 Datasheet
242Kb / 26P
   3.3 VOLT CMOS SuperSync FIFOTM
IDT72255LA IDT-IDT72255LA Datasheet
354Kb / 27P
   CMOS SUPERSYNC FIFO
DT72281 IDT-DT72281_13 Datasheet
424Kb / 26P
   CMOS SuperSync FIFO
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27


Datasheet Download

Go To PDF Page


Link URL




Privacy Policy
ALLDATASHEET.NET
Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com