LTC1955

1

sn1955 1955fs

APPLICATIO S

FEATURES

DESCRIPTIO

TYPICAL APPLICATIO

The LTC

power control functions for two smart cards, two S.A.M.

cards or a combination of S.A.M. and smart cards. It

provides a charge pump for battery powered applications

as well as all necessary level shifting circuitry.

The card voltages can be independently set to 1.8V, 3V or

5V. Both card interfaces include a card detection channel

with automatic debounce circuitry. To reduce wiring costs,

the LTC1955 interfaces to a microcontroller via a simple

4-wire serial interface. Multiple devices may be connected

in daisy-chain fashion so that the number of wires to the

card socket board is independent of the number of sock-

ets. Status data is returned over the same interface.

Extensive security features ensure proper deactivation

sequencing in the event of a supply fault or a smart card

electrical fault. The smart card pins can withstand greater

than 10kV ESD in-situ with no additional components.

The LTC1955 is available in a small 5mm

× 5mm QFN

package.

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Handheld Payment Terminals

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Pay Telephones

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ATM Machines

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POS Terminals

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Computer Keyboards

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Multiple S.A.M. Sockets

, LTC and LT are registered trademarks of Linear Technology Corporation.

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Compatible with ISO7816-3 and EMV Electrical

Specifications

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Power Management and Control for Two Smart

Cards

s

Control/Status Serial Port May be Daisy-Chained

for Multicard Applications

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Automatic Shutdown on Electrical Faults

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Buck/Boost Charge Pump Generates 5V, 3V or 1.8V

Outputs (Smart Card Classes A, B and C)*

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Independent 5V/3V/1.8V Level Control for Both Cards

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Automatic Level Translation

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Supervisory Functions Prevent Smart Card Faults

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Low Operating Current: 250

µA Typical

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Ultralow Shutdown Current

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>10kV ESD on Smart Card Pins

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Small 32-Pin 5mm

× 5mm QFN Package

Dual Smart Card Interface

with Serial Control

4-WIRE

COMMAND

INTERFACE

4-WIRE

CARD

INTERFACE

SMART CARD

VENDOR CARD

C8A

C4A

I/O A

RST A

CLK A

PRES B

3

4

5

6

7

8

21

2

CARD

DETECT

23

20

19

18

17

15

11

14

24

1

12,13

9, 10

29

30

32

31

22

27

28

26

25

I/O B

RST B

CLK B

GND

FAULT

SCLK

LD

DATA

SYNC

ASYNC

NC/NO

PRES A

UNDERV

240k

LTC1955

1

µF

1

µF

4.7

µF

1955 TA01

1

µF

4.7

µF

0.1

µF

CPO

180k

INPUT

POWER

RST A

5V/DIV

10

µs/DIV

1955 G11.eps

Deactivation Sequence

I/O A

5V/DIV

5V/DIV

CLK A

5V/DIV

*U.S. Patent No. 6,411,531