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MAX1162BE_B Datasheet(PDF) 7 Page - Maxim Integrated Products |
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MAX1162BE_B Datasheet(HTML) 7 Page - Maxim Integrated Products |
7 / 17 page Detailed Description The MAX1162 includes an input track-and-hold (T/H) and successive-approximation register (SAR) circuitry to convert an analog input signal to a digital 16-bit out- put. Figure 4 shows the MAX1162 in its simplest config- uration. The serial interface requires only three digital lines (SCLK, CS, and DOUT) and provides an easy interface to microprocessors (µPs). The MAX1162 has two power modes: normal and shut- down. Driving CS high places the MAX1162 in shut- down, reducing the supply current to 0.1µA (typ), while pulling CS low places the MAX1162 in normal operating mode. Falling edges on CS initiate conversions that are driven by SCLK. The conversion result is available at DOUT in unipolar serial format. The serial data stream consists of eight zeros followed by the data bits (MSB first). Figure 3 shows the interface timing diagram. Analog Input Figure 5 illustrates the input sampling architecture of the ADC. The voltage applied at REF sets the full-scale input voltage. Track-and-Hold (T/H) In track mode, the analog signal is acquired on the internal hold capacitor. In hold mode, the T/H switches open and the capacitive DAC samples the analog input. During the acquisition, the analog input (AIN) charges capacitor CDAC. The acquisition interval ends on the falling edge of the sixth clock cycle (Figure 6). At this instant, the T/H switches open. The retained charge on CDAC represents a sample of the input. In hold mode, the capacitive digital-to-analog converter (DAC) adjusts during the remainder of the conversion cycle to restore node ZERO to zero within the limits of 16-bit resolution. At the end of the conversion, force CS high and then low to reset the input side of the CDAC switches back to AIN, and charge CDAC to the input signal again. The time required for the T/H to acquire an input signal is a function of how quickly its input capacitance is charged. If the input signal’s source impedance is high, the acquisition time lengthens and more time must be allowed between conversions. The acquisition time (tACQ) is the maximum time the device takes to acquire the signal. Use the following formula to calculate acqui- sition time: tACQ = 13(RS + RIN) x 35pF where RIN = 800 Ω, RS = the input signal’s source impedance, and tACQ is never less than 1.1µs. A source impedance less than 1k Ω does not significantly affect the ADC’s performance. To improve the input signal bandwidth under AC condi- tions, drive AIN with a wideband buffer (>4MHz) that can drive the ADC’s input capacitance and settle quickly. 16-Bit, +5V, 200ksps ADC with 10µA Shutdown _______________________________________________________________________________________ 7 Pin Description PIN NAME FUNCTION 1 REF External Reference Voltage Input. Sets the analog voltage range. Bypass to AGND with a 4.7µF capacitor. 2AVDD Analog +5V Supply Voltage. Bypass to AGND (pin 3) with a 0.1µF capacitor. 3, 9 AGND Analog Ground. Connect pins 3 and 9 together. Place star ground at pin 3. 4 CS Active-Low Chip-Select Input. Forcing CS high places the MAX1162 in shutdown with a typical current of 0.1µA. A high-to-low transition on CS activates normal operating mode and initiates a conversion. 5 SCLK Serial Clock Input. SCLK drives the conversion process and clocks out data at data rates up to 4.8MHz. 6 DOUT Serial Data Output. Data changes state on SCLK’s falling edge. DOUT is high impedance when CS is high. 7 DGND Digital Ground 8DVDD Digital Supply Voltage. Bypass to DGND with a 0.1µF capacitor. 10 AIN Analog Input |
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