MPC755BRX350LE datasheet(6/56 Pages) MOTOROLA

Part #	MPC755BRX350LE

Description	RISC Microprocessor Hardware Specifications

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Manufacturer	MOTOROLA [Motorola, Inc]

Direct Link	http://www.freescale.com

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MPC755 RISC Microprocessor Hardware Specifications, Rev. 6.1

6

Freescale Semiconductor

General Parameters

— Parity checking on both L2 address and data

•

Memory management unit

— 128-entry, two-way set-associative instruction TLB

— 128-entry, two-way set-associative data TLB

— Hardware reload for TLBs

— Hardware or optional software tablewalk support

— Eight instruction BATs and eight data BATs

— Eight SPRGs, for assistance with software tablewalks

— Virtual memory support for up to 4 exabytes (252) of virtual memory

— Real memory support for up to 4 gigabytes (232) of physical memory

•

Bus interface

— Compatible with 60x processor interface

— 32-bit address bus

— 64-bit data bus, 32-bit mode selectable

— Bus-to-core frequency multipliers of 2x, 3x, 3.5x, 4x, 4.5x, 5x, 5.5x, 6x, 6.5x, 7x, 7.5x, 8x, 10x

supported

— Selectable interface voltages of 2.5 and 3.3 V

— Parity checking on both address and data buses

•

Power management

— Low-power design with thermal requirements very similar to MPC740/MPC750

— Three static power saving modes: doze, nap, and sleep

— Dynamic power management

•

Integrated thermal management assist unit

— On-chip thermal sensor and control logic

— Thermal management interrupt for software regulation of junction temperature

•

Testability

— LSSD scan design

— IEEE 1149.1 JTAG interface

3 General Parameters

The following list provides a summary of the general parameters of the MPC755:

Technology

0.22 µm CMOS, six-layer metal

Die size

6.61 mm

× 7.73 mm (51 mm2)

Transistor count

6.75 million

Logic design

Fully-static

Packages

MPC745: Surface mount 255 plastic ball grid array (PBGA)

MPC755: Surface mount 360 ceramic ball grid array (CBGA)

Surface mount 360 plastic ball grid array (PBGA)

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MPC755BRX350LE Datasheet(PDF) 6 Page - Motorola, Inc

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