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MSC1201Y2 Datasheet(PDF) 5 Page - Burr-Brown (TI) |
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MSC1201Y2 Datasheet(HTML) 5 Page - Burr-Brown (TI) |
5 / 78 page MSC1201 MSC1202 SBAS317B − APRIL 2004 − REVISED JANUARY 2005 www.ti.com 5 ELECTRICAL CHARACTERISTICS: AVDD = 3V All specifications from TMIN to TMAX, DVDD = +2.7V to +5.25V, fMOD = 15.625kHz, PGA = 1, Buffer ON, fDATA = 10Hz, Bipolar, and VREF ≡ (REF IN+) − (REF IN−) = +1.25V, unless otherwise noted. MSC1201Yx, MSC1202Yx PARAMETER CONDITIONS MIN TYP MAX UNITS Analog Input (AIN0-AIN5, AINCOM) Analog Input Range Buffer OFF AGND − 0.1 AVDD + 0.1 V Analog Input Range Buffer ON AGND + 50mV AVDD − 1.5 V Full-Scale Input Voltage Range (In+) − (In−) ±VREF/PGA V Differential Input Impedance Buffer OFF 7/PGA(1) M Ω Input Current Buffer ON 0.5 nA Fast Settling Filter −3dB 0.469 • fDATA Bandwidth Sinc2 Filter −3dB 0.318 • fDATA Bandwidth Sinc3 Filter −3dB 0.262 • fDATA Programmable Gain Amplifier User-Selectable Gain Range 1 128 Input Capacitance Buffer ON 7 pF Input Leakage Current Multiplexer Channel Off, T = +25 °C 0.5 pA Burnout Current Sources Buffer ON ±2 µA ADC Offset DAC Offset DAC Range ±VREF/(2 • PGA) V Offset DAC Resolution 8 Bits Offset DAC Full-Scale Gain Error ±1.5 % of Range Offset DAC Full-Scale Gain Error Drift 0.6 ppm/ °C System Performance Resolution MSC1201 24 Bits Resolution MSC1202 16 Bits ENOB MSC1201 22 Bits ENOB MSC1202 16 Bits Output Noise See Typical Characteristics No Missing Codes MSC1201, Sinc3 Filter, Decimation > 360 24 Bits No Missing Codes MSC1202, Sinc3 Filter 16 Bits Integral Nonlinearity End Point Fit, Differential Input ±0.0004 ±0.0015 % of FSR Offset Error After Calibration 1.3 ppm of FS Offset Drift(2) Before Calibration 0.02 ppm of FS/ °C Gain Error(3) After Calibration 0.005 % Gain Error Drift(2) Before Calibration 0.5 ppm/ °C System Gain Calibration Range 80 120 % of FS System Offset Calibration Range −50 50 % of FS At DC 130 dB Common-Mode Rejection fCM = 60Hz, fDATA = 10Hz 130 dB Common-Mode Rejection fCM = 50Hz, fDATA = 50Hz 120 dB fCM = 60Hz, fDATA = 60Hz 120 dB Normal-Mode Rejection fSIG = 50Hz, fDATA = 50Hz 100 dB Normal-Mode Rejection fSIG = 60Hz, fDATA = 60Hz 100 dB Power-Supply Rejection At DC, dB = −20log( ∆VOUT/∆VDD)(4) 88 dB (1) The input impedance for PGA = 128 is the same as that for PGA = 64 (that is, 7MΩ/64). (2) Calibration can minimize these errors. (3) The gain calibration cannot have a REF IN+ of more than AVDD −1.5V with Buffer ON. To calibrate gain, turn Buffer OFF. (4) ∆VOUT is change in digital result. |
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