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NB100LVEP56MNG Datasheet(PDF) 1 Page - ON Semiconductor

Part # NB100LVEP56MNG
Description  2.5V / 3.3V / 5V ECL Dual Differential 2:1 Multiplexer
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Manufacturer  ONSEMI [ON Semiconductor]
Direct Link  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

NB100LVEP56MNG Datasheet(HTML) 1 Page - ON Semiconductor

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 Semiconductor Components Industries, LLC, 2004
December, 2004 − Rev. 5
1
Publication Order Number:
NB100LVEP56/D
NB100LVEP56
2.5V / 3.3V / 5VECL Dual
Differential 2:1 Multiplexer
The NB100LVEP56 is a dual, fully differential 2:1 multiplexer. The
differential data path makes the device ideal for multiplexing low
skew clock or differential data signals. The device features both
individual and common select inputs to address both data path and
random logic applications. Common and individual selects can accept
both ECL and CMOS input voltage levels. Multiple VBB pins are
provided.
The VBB pin, an internally generated voltage supply, is available to
this device only. For single−ended input operation, the unused
differential input is connected to VBB as a switching reference voltage.
VBB may also rebias AC coupled inputs. When used, decouple VBB
and VCC via a 0.01 mF capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, VBB should be left open.
Maximum Input Clock Frequency > 2.5 GHz Typical
Maximum Input Data Rate > 2.5 Gb/s Typical
525 ps Typical Propagation Delays
Low Profile QFN Package
PECL Mode Operating Range:
VCC = 2.375 V to 5.5 V with VEE = 0 V
NECL Mode Operating Range:
VCC = 0 V with VEE = −2.375 V to −5.5 V
Separate, Common Select, and Individual Select
(Compatible with ECL and CMOS Input Voltage Levels)
Q Output Will Default LOW with Inputs Open or at VEE
Multiple VBB Outputs
Pb−Free Packages are Available*
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
TSSOP−20
DT SUFFIX
CASE 948E
MARKING
DIAGRAMS*
*For additional information, see Application Note
AND8002/D
N100
VP56
ALYW
20
1
1
20
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
N100
VP56
ALYW
1
24
QFN−24
MN SUFFIX
CASE 485L
24
1
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
ORDERING INFORMATION
http://onsemi.com


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