NT5DS64M4AT NT5DS64M4AW

NT5DS32M8AT NT5DS32M8AW

256Mb DDR333/300 SDRAM

Preliminary

10/01

1

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Features

• Double data rate architecture: two data transfers per

clock cycle

• Bidirectional data strobe (DQS) is transmitted and

received with data, to be used in capturing data at the

receiver

• DQS is edge-aligned with data for reads and is center-

aligned with data for writes

• Differential clock inputs (CK and CK)

• Four internal banks for concurrent operation

• Data mask (DM) for write data

• DLL aligns DQ and DQS transitions with CK transitions.

• Commands entered on each positive CK edge; data and

data mask referenced to both edges of DQS

• Burst lengths: 2, 4, or 8

• CAS Latency: 2, 2.5

• Auto Precharge option for each burst access

• Auto Refresh and Self Refresh Modes

• 7.8

µs Maximum Average Periodic Refresh Interval

• 2.5V (SSTL_2 compatible) I/O

• Package : 66pin TSOP-II / 60 balls 0.8mmx1.0mm pitch

CSP.

Description

The 256Mb DDR SDRAM is a high-speed CMOS, dynamic

random-access memory containing 268,435,456 bits. It is

internally configured as a quad-bank DRAM.

The 256Mb DDR SDRAM uses a double-data-rate architec-

ture to achieve high-speed operation. The double data rate

architecture is essentially a 2n prefetch architecture with an

interface designed to transfer two data words per clock cycle

at the I/O pins. A single read or write access for the 256Mb

DDR SDRAM effectively consists of a single 2n-bit wide, one

clock cycle data transfer at the internal DRAM core and two

corresponding n-bit wide, one-half-clock-cycle data transfers

at the I/O pins.

A bidirectional data strobe (DQS) is transmitted externally,

along with data, for use in data capture at the receiver. DQS

is a strobe transmitted by the DDR SDRAM during Reads

and by the memory controller during Writes. DQS is edge-

aligned with data for Reads and center-aligned with data for

Writes.

The 256Mb DDR SDRAM operates from a differential clock

(CK and CK; the crossing of CK going high and CK going

LOW is referred to as the positive edge of CK). Commands

(address and control signals) are registered at every positive

edge of CK. Input data is registered on both edges of DQS,

and output data is referenced to both edges of DQS, as well

as to both edges of CK.

Read and write accesses to the DDR SDRAM are burst ori-

ented; accesses start at a selected location and continue for

a programmed number of locations in a programmed

sequence. Accesses begin with the registration of an Active

command, which is then followed by a Read or Write com-

mand. The address bits registered coincident with the Active

command are used to select the bank and row to be

accessed. The address bits registered coincident with the

Read or Write command are used to select the bank and the

starting column location for the burst access.

The DDR SDRAM provides for programmable Read or Write

burst lengths of 2, 4 or 8 locations. An Auto Precharge func-

tion may be enabled to provide a self-timed row precharge

that is initiated at the end of the burst access.

As with standard SDRAMs, the pipelined, multibank architec-

ture of DDR SDRAMs allows for concurrent operation,

thereby providing high effective bandwidth by hiding row pre-

charge and activation time.

An auto refresh mode is provided along with a power-saving

power-down mode. All inputs are compatible with the JEDEC

Standard for SSTL_2. All outputs are SSTL_2, Class II com-

patible.

CAS Latency and Frequency

CAS Latency

Maximum Operating Frequency (MHz)*

DDR333 (-6)

DDR300 (-66)

2

133

133

2.5

166

150