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VSP2270 Datasheet(PDF) 7 Page - Texas Instruments |
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VSP2270 Datasheet(HTML) 7 Page - Texas Instruments |
7 / 19 page VSP2270 SLES019 – DECEMBER 2001 7 www.ti.com timing specification VSP2270 CDS CCD Output Signal SHP (See Note 9) SHD (See Note 9) ADCCK B[9:0] N+1 N N+2 N+3 tw(P) tw(D) t(PD) t(DP) t(S) t(S) t(CKP) t(CKP) t(CKP) t(ADC) t(ADC) t(INHIBIT) th(O) td(O) N–10 N–11 N–9N–8N–7 SYMBOL PARAMETER MIN TYP MAX UNIT t(CKP) Clock period 35 ns t(ADC) ADCCK high/low pulse width 17 ns tw(P) SHP pulse width 8 ns tw(D) SHD pulse width 8 ns t(PD) SHP trailing edge to SHD leading edge (see Note 9) 8 ns t(DP) SHD trailing edge to SHP leading edge (see Note 9) 8 ns t(S) Sampling delay 3 ns t(INHIBIT) Inhibited clock period 20 ns th(O) Output hold time 2 ns td(O) Output delay (no load) 22 ns DL Data latency, normal operation mode 9 (fixed) Clock Cycles NOTES: 9. The description and the timing diagrams in this data sheet are all based on the polarity of active low (default value). 10. The user can select the active polarity (active low or active high) through the serial interface, refer to the serial interface section for details. 11. Output hold time is specified at additional output delay = 0 ns, refer to the serial interface section for details. |
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