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XRT83SL314 Datasheet(PDF) 4 Page - Exar Corporation |
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XRT83SL314 Datasheet(HTML) 4 Page - Exar Corporation |
4 / 85 page XRT83SL314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT REV. P1.0.5 PRELIMINARY I TABLE OF CONTENTS GENERAL DESCRIPTION.............................................................................................................. 1 APPLICATIONS .......................................................................................................................................................... 1 FIGURE 1. BLOCK DIAGRAM OF THE XRT83SL314.................................................................................................................................. 1 FEATURES ..................................................................................................................................................................... 2 PRODUCT ORDERING INFORMATION ..................................................................................................2 PIN OUT OF THE XRT83SL314 ..................................................................................................... 3 TABLE OF CONTENTS ............................................................................................................I PIN DESCRIPTIONS....................................................................................................................... 3 MICROPROCESSOR ........................................................................................................................................................ 3 RECEIVER SECTION ....................................................................................................................................................... 4 TRANSMITTER SECTION.................................................................................................................................................. 7 CONTROL FUNCTION...................................................................................................................................................... 9 CLOCK SECTION ............................................................................................................................................................ 9 POWER AND GROUND .................................................................................................................................................. 10 NO CONNECTS ............................................................................................................................................................ 12 1.0 CLOCK SYNTHESIZER .......................................................................................................................13 TABLE 1: INPUT CLOCK SOURCE SELECT .............................................................................................................................................. 13 FIGURE 2. SIMPLIFIED BLOCK DIAGRAM OF THE CLOCK SYNTHESIZER................................................................................................... 14 1.1 ALL T1/E1 MODE ........................................................................................................................................... 14 2.0 RECEIVE PATH LINE INTERFACE .....................................................................................................14 FIGURE 3. SIMPLIFIED BLOCK DIAGRAM OF THE RECEIVE PATH ............................................................................................................ 14 2.1 LINE TERMINATION (RTIP/RRING) .............................................................................................................. 15 2.1.1 CASE 1: INTERNAL TERMINATION.......................................................................................................................... 15 FIGURE 4. TYPICAL CONNECTION DIAGRAM USING INTERNAL TERMINATION .......................................................................................... 15 TABLE 2: SELECTING THE INTERNAL IMPEDANCE.................................................................................................................................... 15 2.1.2 CASE 2: INTERNAL TERMINATION WITH ONE EXTERNAL FIXED RESISTOR FOR ALL MODES..................... 16 FIGURE 5. TYPICAL CONNECTION DIAGRAM USING ONE EXTERNAL FIXED RESISTOR.............................................................................. 16 TABLE 3: SELECTING THE VALUE OF THE EXTERNAL FIXED RESISTOR.................................................................................................... 16 2.2 EQUALIZER CONTROL ................................................................................................................................. 17 FIGURE 6. SIMPLIFIED BLOCK DIAGRAM OF THE EQUALIZER AND PEAK DETECTOR ................................................................................. 17 2.3 CABLE LOSS INDICATOR ............................................................................................................................. 17 FIGURE 7. SIMPLIFIED BLOCK DIAGRAM OF THE CABLE LOSS INDICATOR................................................................................................ 17 2.4 EQUALIZER ATTENUATION FLAG .............................................................................................................. 18 FIGURE 8. SIMPLIFIED BLOCK DIAGRAM OF THE EQUALIZER ATTENUATION FLAG .................................................................................... 18 2.5 PEAK DETECTOR AND SLICER ................................................................................................................... 18 TABLE 4: SELECTING THE SLICER LEVEL FOR THE PEAK DETECTOR....................................................................................................... 18 2.6 CLOCK AND DATA RECOVERY ................................................................................................................... 19 FIGURE 9. RECEIVE DATA UPDATED ON THE RISING EDGE OF RCLK..................................................................................................... 19 FIGURE 10. RECEIVE DATA UPDATED ON THE FALLING EDGE OF RCLK................................................................................................. 19 2.6.1 RECEIVE SENSITIVITY .............................................................................................................................................. 20 FIGURE 11. TEST CONFIGURATION FOR MEASURING RECEIVE SENSITIVITY ............................................................................................ 20 TABLE 5: TIMING SPECIFICATIONS FOR RCLK/RPOS/RNEG.................................................................................................................20 2.6.2 INTERFERENCE MARGIN ......................................................................................................................................... 21 FIGURE 12. TEST CONFIGURATION FOR MEASURING INTERFERENCE MARGIN......................................................................................... 21 2.6.3 GENERAL ALARM DETECTION AND INTERRUPT GENERATION ........................................................................ 21 FIGURE 13. INTERRUPT GENERATION PROCESS BLOCK ......................................................................................................................... 21 2.6.3.1 RLOS (RECEIVER LOSS OF SIGNAL) ..................................................................................................................... 21 FIGURE 14. ANALOG RECEIVE LOS OF SIGNAL FOR T1/E1/J1................................................................................................................ 22 2.6.3.2 EXLOS (EXTENDED LOSS OF SIGNAL) .................................................................................................................. 22 2.6.3.3 AIS (ALARM INDICATION SIGNAL) ......................................................................................................................... 22 TABLE 6: ANALOG RLOS DECLARE/CLEAR (TYPICAL VALUES) FOR T1/E1 ............................................................................................. 22 2.6.3.4 NLCD (NETWORK LOOP CODE DETECTION) .......................................................................................................... 23 FIGURE 15. PROCESS BLOCK FOR AUTOMATIC LOOP CODE DETECTION ................................................................................................ 23 2.6.3.5 FLSD (FIFO LIMIT STATUS DETECTION) ............................................................................................................... 24 2.6.3.6 LCVD (LINE CODE VIOLATION DETECTION) ........................................................................................................... 24 2.7 RECEIVE JITTER ATTENUATOR .................................................................................................................. 24 2.8 HDB3/B8ZS DECODER .................................................................................................................................. 24 2.9 RPOS/RNEG/RCLK ........................................................................................................................................ 25 FIGURE 16. SINGLE RAIL MODE WITH A FIXED REPEATING "0011" PATTERN ......................................................................................... 25 |
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