Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.NET

X  

XRT7295ATIW Datasheet(PDF) 11 Page - Exar Corporation

Part # XRT7295ATIW
Description  DS3/Sonet STS-1 Integrated Line Receiver
Download  18 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  EXAR [Exar Corporation]
Direct Link  http://www.exar.com
Logo EXAR - Exar Corporation

XRT7295ATIW Datasheet(HTML) 11 Page - Exar Corporation

Back Button XRT7295ATIW Datasheet HTML 7Page - Exar Corporation XRT7295ATIW Datasheet HTML 8Page - Exar Corporation XRT7295ATIW Datasheet HTML 9Page - Exar Corporation XRT7295ATIW Datasheet HTML 10Page - Exar Corporation XRT7295ATIW Datasheet HTML 11Page - Exar Corporation XRT7295ATIW Datasheet HTML 12Page - Exar Corporation XRT7295ATIW Datasheet HTML 13Page - Exar Corporation XRT7295ATIW Datasheet HTML 14Page - Exar Corporation XRT7295ATIW Datasheet HTML 15Page - Exar Corporation Next Button
Zoom Inzoom in Zoom Outzoom out
 11 / 18 page
background image
XRT7295AT
11
Rev.1.20
JITTER ACCOMMODATION
Under all allowable operating conditions, the jitter
accommodation of the XRT7295AT device exceeds all
system
requirements
for
error-free
operation
(BER<1E-9). The typical (VDD = 5V, T = 25°C, DSX-3
nominal signal level) jitter accommodation for the
XRT7295AT is shown in Figure 10.
FALSE-LOCK IMMUNITY
False-lock is defined as the condition where a PLL
recovered clock obtains stable phase-lock at a frequency
not equal to the incoming data rate. The XRT7295AT
device uses a combination frequency/phase-lock
architecture to prevent false-lock. An on-chip frequency
comparator continuously compares the EXCLK reference
to the PLL clock. If the frequency difference between the
EXCLK and PLL clock exceeds approximately ±0.5%,
correction circuitry forces re-acquisition of the proper
frequency and phase.
ACQUISITION TIME
If a valid input signal is assumed to be already present at
RIN, the maximum time between the application of device
power and error-free operation is 20ms. If power has
already been applied, the interval between the application
of valid data (or the action of valid data following a loss of
signal) and error-free operation is 4ms.
LOSS-OF-LOCK DETECTION
As stated above, the PLL acquisition aid circuitry monitors
the PLL clock frequency relative to the EXCLK frequency.
The RLOL alarm is activated if the difference between the
PLL clock and the EXCLK frequency exceeds
approximately ±0.5%.
This will not occur until at least 250 bit periods after loss of
input data.
Figure 9. Typical PLL Jitter Transfer
Characteristic
1
0
-5
-4
-3
-2
-1
100
500 1K
5K 10K
50K100K 500K
PEAK = 0.05dB
f3dB = 205kHz
Frequency (Hz)
1
10
100
1K
10K
100K
1000K
40
10
1.0
0.1
XRT7295AT Typical
PUB 54014
G.824
TR-TSY-000499
Category 1
TR-TSY-000499
Category 2
5k
10
10k
5
60k
1
300k
0.5
1M
0.4
XRT7295AT Typical
Sinewave Jitter Frequency (Hz)
Figure 10. Input Jitter Tolerance at DSX-3 Level
Jitter
Frequency
(Hz)
Jitter
Amplitude
(U.I.)


Similar Part No. - XRT7295ATIW

ManufacturerPart #DatasheetDescription
logo
Exar Corporation
XRT7295ATIW-F EXAR-XRT7295ATIW-F Datasheet
123Kb / 2P
   DS3 SONET STS1 Integrated Line Receiver
More results

Similar Description - XRT7295ATIW

ManufacturerPart #DatasheetDescription
logo
Exar Corporation
XRT7295AE EXAR-XRT7295AE Datasheet
1Mb / 18P
   DS3/Sonet STS-1 Integrated Line Receiver
XR-T7295 EXAR-XR-T7295 Datasheet
226Kb / 20P
   DS3/Sonet STS-1 Integrated Line Receiver
XRT7295AT EXAR-XRT7295AT_10 Datasheet
123Kb / 2P
   DS3 SONET STS1 Integrated Line Receiver
logo
Asahi Kasei Microsystem...
AK2500B AKM-AK2500B Datasheet
78Kb / 17P
   DS3/STS-1 Analog Line Receiver
logo
Exar Corporation
XRT75VL00D EXAR-XRT75VL00D_08 Datasheet
842Kb / 92P
   E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET
XR-T7296 EXAR-XR-T7296 Datasheet
173Kb / 16P
   DS3/STS-1, E3 Integrated Line Transmitter
XRT7298 EXAR-XRT7298 Datasheet
582Kb / 16P
   DS3/STS-1, E3 INTEGRATED LINE TRANSMITTER
XRT75L00D EXAR-XRT75L00D Datasheet
894Kb / 92P
   E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
XRT75VL00D EXAR-XRT75VL00D Datasheet
836Kb / 92P
   E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
XRT7296 EXAR-XRT7296_10 Datasheet
124Kb / 2P
   XRT7296 DS3 STS-1 E3 Integrated Line Transmitter
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18


Datasheet Download

Go To PDF Page


Link URL




Privacy Policy
ALLDATASHEET.NET
Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com