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IDT79RV5000180G Datasheet(PDF) 9 Page - Integrated Device Technology |
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IDT79RV5000180G Datasheet(HTML) 9 Page - Integrated Device Technology |
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9 / 15 page  9 of 15 April 10, 2001 79RC5000 CCCCapac apac apac apaciti iti iti itivvvveeee Load Deration—RC500 Load Deration—RC500 Load Deration—RC500 Load Deration—RC5000000 6\VWHP ,QWHUIDFH 6\VWHP ,QWHUIDFH 6\VWHP ,QWHUIDFH 6\VWHP ,QWHUIDFH 3 3 3 3D DD DUD UD UD UDPHWH PHWH PHWH PHWHUUUUV³ V³ V³ V³5 5 5 5& & & & Note: 50 pf loading on external output signals % % % %RRW 7LPH , RRW 7LPH , RRW 7LPH , RRW 7LPH ,Q QQ QWHU WHU WHU WHUIIIIDFH 3D DFH 3D DFH 3D DFH 3DUUUUDPHWH DPHWH DPHWH DPHWHUUUUVVVV³ ³ ³ ³5 5 5 5& & & & 3DUDPHWHU 6\PERO 7HVW &RQGLWLRQV 0+] 0+] 0+] 8QLWV MinMax MinMax MinMax Load Derate CLD —— 2 — 2 — 2 ns/25pF 3DUDPHWHU 6\PERO 7HVW &RQGLWLRQV 0+] SLSHOLQH 0+] %XV )UHTXHQF\ 0+] SLSHOLQH 0+] %XV )UHTXHQF\ 0+] SLSHOLQH 0+] %XV )UHTXHQF\ 8QLWV Min Max Min Max Min Max Data Output tDO = Max tDM = Min mode14..13 = 10 (fastest, 100%) 0 1 1. Guaranteed by design. 701 501 4.7 ns mode14..13 = 11 (83%) 01 801 701 5ns mode14..13 = 00 (67%) 01 901 901 6ns mode14..13 = 01 (slowest, 50%) 0 1 11 01 11 01 7ns Data Output Hold tDOH 1 mode14..13 = 10 (fastest) 0 — 0 — 0 — ns mode14..13 = 11 (83%) 0 — 0 — 0 — ns mode14..13 = 00 (67%) 0 — 0 — 0 — ns mode14..13 = 01 (slowest) 0 — 0 — 0 — ns Data Input tDS trise = 3ns tfall = 3ns 1.5 — 1.5 — 1.5 — ns tDH 0.5 — 0.5 — 0.5 — ns 3DUDPHWHU 6\PERO 7HVW &RQGLWLRQV 0+] 0+] 0+] 0+] 0+] 0+] 8QLWV &RQGLWLRQV Min Max Min Max Min Max Mode Data Setup tDS — 4 — 4 — 4 — ns Master Clock Cycle Mode Data Hold tDH — 0 — 0 — 0 — ns Master Clock Cycle |
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