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ADSP-21161NCCA-100 Datasheet(PDF) 9 Page - Analog Devices |
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ADSP-21161NCCA-100 Datasheet(HTML) 9 Page - Analog Devices |
9 / 60 page –9– REV. A ADSP-21161N The serial ports operate at up to half the clock rate of the core, providing each with a maximum data rate of 50 M bit/s. The serial data pins are programmable as either a transmitter or receiver, providing greater flexibility for serial communications. Serial port data can be automatically transferred to and from on-chip memory via a dedicated DMA. Each of the serial ports features a Time Division Multiplex (TDM) multichannel mode, where two serial ports are TDM transmitters and two serial ports are TDM receivers (SPORT0 Rx paired with SPORT2 Tx, SPORT1 Rx paired with SPORT3 Tx). Each of the serial ports also support the I 2S protocol (an industry standard interface commonly used by audio codecs, ADCs and DACs), with two data pins, allowing four I 2S channels (using two I2S stereo devices) per serial port, with a maximum of up to 16 I 2S channels. The serial ports permit little-endian or big-endian transmission formats and word lengths selectable from 3 bits to 32 bits. For I 2S mode, data-word lengths are selectable between 8 bits and 32 bits. Serial ports offer selectable synchronization and transmit modes as well as optional µ-law or A-law companding. Serial port clocks and frame syncs can be internally or externally generated. Serial Peripheral (Compatible) Interface Serial Peripheral Interface (SPI) is an industry standard synchro- nous serial link, enabling the ADSP-21161N SPI-compatible port to communicate with other SPI-compatible devices. SPI is a 4-wire interface consisting of two data pins, one device select pin, and one clock pin. It is a full-duplex synchronous serial interface, supporting both master and slave modes. The SPI port can operate in a multimaster environment by interfacing with up to four other SPI-compatible devices, either acting as a master or slave device. The ADSP-21161N SPI-compatible peripheral implementation also features programmable baud rate and clock phase/polarities. The ADSP-21161N SPI-compatible port uses open drain drivers to support a multimaster configuration and to avoid data contention. Host Processor Interface The ADSP-21161N host interface enables easy connection to standard 8-bit, 16-bit, or 32-bit microprocessor buses with little additional hardware required. The host interface is accessed through the ADSP-21161N’s external port. Four channels of DMA are available for the host interface; code and data transfers are accomplished with low software overhead. The host processor requests the ADSP-21161N’s external bus with the host bus request ( HBR), host bus grant (HBG), and chip select (CS) signals. The host can directly read and write the internal IOP registers of the ADSP-21161N, and can access the DMA channel setup and message registers. DMA setup via a host would allow it to access any internal memory address via DMA transfers. Vector interrupt support provides efficient execution of host commands. General-Purpose I/O Ports The ADSP-21161N also contains 12 programmable, general purpose I/O pins that can function as either input or output. As output, these pins can signal peripheral devices; as input, these pins can provide the test for conditional branching. Program Booting The internal memory of the ADSP-21161N can be booted at system power-up from either an 8-bit EPROM, a host processor, the SPI interface, or through one of the link ports. Selection of the boot source is controlled by the Boot Memory Select ( BMS), EBOOT (EPROM Boot), and Link/Host Boot (LBOOT) pins. 8-, 16-, or 32-bit host processors can also be used for booting. Phase-Locked Loop and Crystal Double Enable The ADSP-21161N uses an on-chip Phase-Locked Loop (PLL) to generate the internal clock for the core. The CLK_CFG1 –0 pins are used to select ratios of 2:1, 3:1, and 4:1. In addition to the PLL ratios, the CLKDBL pin can be used for more clock ratio options. The (1 ×/2× CLKIN) rate set by the CLKDBL pin determines the rate of the PLL input clock and the rate at which the external port operates. With the combination of CLK_CFG1 –0 and CLKDBL, ratios of 2:1, 3:1, 4:1, 6:1, and 8:1 between the core and CLKIN are supported. See also Figure 10 on Page 20. Power Supplies The ADSP-21161N has separate power supply connections for the analog (AVDD/AGND), internal (VDDINT), and external (VDDEXT) power supplies. The internal and analog supplies must meet the 1.8 V requirement. The external supply must meet the 3.3 V requirement. All external supply pins must be connected to the same supply. Note that the analog supply (AVDD) powers the ADSP-21161N’s clock generator PLL. To produce a stable clock, provide an external circuit to filter the power input to the AVDD pin. Place the filter as close as possible to the pin. For an example circuit, see Figure 5. To prevent noise coupling, use a wide trace for the analog ground (AGND) signal and install a decoupling capacitor as close as possible to the pin. Development Tools The ADSP-21161N is supported with a complete set of software and hardware development tools, including Analog Devices emulators and VisualDSP++ 1 development environment. The same emulator hardware that supports other ADSP-21xxx DSPs, also fully emulates the ADSP-21161N. The VisualDSP++ project management environment lets pro- grammers develop and debug an application. This environment includes an easy-to-use assembler that is based on an algebraic syntax; an archiver (librarian/library builder), a linker, a loader, Figure 5. Analog Power (AVDD) Filter Circuit 1 VisualDSP++ is a registered trademark of Analog Devices, Inc. 10 VDDINT 0.1 F 0.01 F AGND AVDD |
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