CY7C1393AV18 datasheet(11/21 Pages) CYPRESS

Part #	CY7C1393AV18

Description	18-Mbit DDR-II SIO SRAM 2-Word Burst Architecture

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Manufacturer	CYPRESS [Cypress Semiconductor]

Direct Link	http://www.cypress.com

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11 / 21 page

PRELIMINARY

CY7C1392AV18

CY7C1393AV18

CY7C1394AV18

Document #: 38-05503 Rev. *A

Page 11 of 21

tCCQO

tCHCQV

C/C Clock Rise to Echo Clock Valid

–

0.45

–

0.45

–

0.50

ns

tCQOH

tCHCQX

Echo Clock Hold after C/C Clock Rise

–0.45

–

–0.45

–

–0.50

–

ns

tCQD

tCQHQV

Echo Clock High to Data Change

–

0.30

–

0.35

–

0.40

ns

tCQDOH

tCQHQX

Echo Clock High to Data Change

–0.30

–

–0.35

–

–0.40

–

ns

tCHZ

Clock (C and C) Rise to High-Z (

Active to High-Z)[19, 20]

–

0.45

–

0.45

–0.50ns

tCLZ

Clock (C and C) Rise to Low-Z[19, 20]

–0.45

–

–0.45

–

–0.50

–

ns

DLL Timing

tKC Var

Clock Phase Jitter

–

0.20

–

0.20

–

0.20

ns

tKC lock

DLL Lock Time (K, C)

1024

–

1024

–

1024

–

Cycles

tKC Reset

K Static to DLL Reset

30

ns

Notes:

19. tCHZ, tCLZ, are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 100 mV from steady-state voltage.

20. At any given voltage and temperature tCHZ is less than tCLZ and tCHZ less than tCO.

Switching Characteristics Over the Operating Range (continued)[17, 18]

Cypress

Parameter

Consortium

Parameter

Description

250 MHz

200 MHz

167 MHz

Unit

Min. Max. Min. Max. Min. Max.

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