PRELIMINARY
18-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1392AV18
CY7C1393AV18
CY7C1394AV18
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
, CA 95134
•
408-943-2600
Document #: 38-05503 Rev. *A
Revised June 1, 2004
Features
• 18-Mbit density (2M x 8, 1M x 18, 512K x 36)
• 250-MHz clock for high bandwidth
• 2-Word burst for reducing address bus frequency
• Double Data Rate (DDR) interfaces (data transferred at
500 MHz) @ 250 MHz
• Two input clocks (K and K) for precise DDR timing
— SRAM uses rising edges only
• Two output clocks (C and C) account for clock skew
and flight time mismatching
• Echo clocks (CQ and CQ) simplify data capture in
high-speed systems
• Synchronous internally self-timed writes
• 1.8V core power supply with HSTL inputs and outputs
• Variable drive HSTL output buffers
• Expanded HSTL output voltage (1.4V–VDD)
• 13 x 15 x 1.4mm 1.0-mm pitch fBGA package, 165 ball
(11 x 15 matrix)
• JTAG 1149.1 compatible test access port
• Delay Lock Loop (DLL) for accurate data placement
Configuration
CY7C1392AV18–2M x 8
CY7C1393AV18–1M x18
CY7C1394AV18–512K x 36
Functional Description
The CY7C1392AV18/CY7C1393AV18/CY7C1394AV18 are
1.8V Synchronous Pipelined SRAMs equipped with DDR-II
SIO (Double Data Rate Separate I/O) architecture. The DDR-II
SIO consists of two separate ports to access the memory
array. The Read port has dedicated Data outputs and the Write
port has dedicated Data inputs to completely eliminate the
need to “turn around’ the data bus required with common I/O
devices. Access to each port is accomplished using a common
address bus. Addresses for Read and Write are latched on
alternate rising edges of the input (K) clock. Write data is regis-
tered on the rising edges of both K and K. Read data is driven
on the rising edges of C and C if provided, or on the rising edge
of K and K if C/C are not provided. Each address location is
associated
with
two
8-bit
words
in
the
case
of
CY7C1392AV18, two 18-bit words in the case of
CY7C1393AV18, and two 36-bit words in the case of
CY7C1394AV18, that burst sequentially into or out of the
device.
Asynchronous inputs include impedance match (ZQ).
Synchronous data outputs are tightly matched to the two
output echo clocks CQ/CQ, eliminating the need for separately
capturing data from each individual DDR-II SIO SRAM in the
system design. Output data clocks (C/C) enable maximum
system clocking and data synchronization flexibility.
All synchronous inputs pass through input registers controlled
by the K/K input clocks. All data outputs pass through output
registers controlled by the C/C input clocks (or K/K in single
clock mode). Writes are conducted with on-chip synchronous
self-timed write circuitry.
Logic Block Diagram (CY7C1392AV18)
1M x 8
CLK
A(19:0)
Gen.
K
K
Control
Logic
Address
Register
D[7:0]
Read Data Reg.
LD
Q[7:0]
Control
Logic
Reg.
Reg.
Reg.
8
8
16
Write
8
BWS0
VREF
Data Reg
Write
Data Reg
Memory
Array
1M x 8
Memory
Array
8
8
20
8
C
C
BWS1
R/W
LD
R/W
CQ
CQ
DOFF
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